diff -Nrcpad gcc-15-20260626/LAST_UPDATED gcc-15-20260703/LAST_UPDATED
*** gcc-15-20260626/LAST_UPDATED	Fri Jun 26 22:32:23 2026
--- gcc-15-20260703/LAST_UPDATED	Fri Jul  3 22:32:22 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-15 revision f27a16df1bb1afb91ba5b388dda9229b545f87ca
--- 1 ----
! Obtained from git: releases/gcc-15 revision cd02f68b56336df7f4d2e358b0fae21dcb5aa6af
diff -Nrcpad gcc-15-20260626/MD5SUMS gcc-15-20260703/MD5SUMS
*** gcc-15-20260626/MD5SUMS	Fri Jun 26 22:32:28 2026
--- gcc-15-20260703/MD5SUMS	Fri Jul  3 22:32:27 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20260626.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20260703.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
*** 25,31 ****
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
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! ef256d681dea816ca8efc091da0ece2a  LAST_UPDATED
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  b714b83dd28679b75c5fd3e619d35956  Makefile.def
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--- 25,31 ----
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*************** c5258891437b4abaf168ed1b1a5b2189  gcc/BA
*** 514,520 ****
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--- 514,520 ----
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*************** fb3fadb88e1d2b3b640cfaaa5ff11780  gcc/Ch
*** 551,557 ****
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! 8ccfafee1087c46b0fea8e36fa916aa3  gcc/DATESTAMP
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--- 551,557 ----
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*************** ec6799501b2eb2923d5de6a66169dbd2  gcc/ON
*** 563,569 ****
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! 7401165a07a0cf9c1799d9a2d43b4d64  gcc/ada/ChangeLog
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--- 563,569 ----
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*************** b042ff9582cb94caab7f476203ea6809  gcc/ad
*** 818,825 ****
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--- 818,825 ----
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*************** e364f4e3ae92066699cc93a8f7b828c1  gcc/ad
*** 2926,2932 ****
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! d66c7c0f7cdacbc9e39c757583ff4ee1  gcc/ada/sem_ch13.adb
  24bb91233702860aa2a308e59ba7cb6a  gcc/ada/sem_ch13.ads
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  2471d629be4739ff5135aa87a2ec9166  gcc/ada/sem_ch2.ads
--- 2926,2932 ----
  1b6f89866a5d427002df059be3847d62  gcc/ada/sem_ch11.ads
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! cd3f40f292d9524a76708f16e5bfc9f1  gcc/ada/sem_ch13.adb
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*************** f28e7beab7cc8baa0b1a2e5e9efc0597  gcc/co
*** 3460,3466 ****
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! cab9211ac73c7480b9b4b45833e20d71  gcc/config/aarch64/aarch64-sve-builtins-base.cc
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  1aedb1965774496622db16f56a477345  gcc/config/aarch64/aarch64-sve-builtins-functions.h
--- 3460,3466 ----
  c39adde4468dd4defbf7200022246f97  gcc/config/aarch64/aarch64-simd.md
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! d3dc8e28c7382c012c8a736183961d6a  gcc/config/aarch64/aarch64-sve-builtins-base.cc
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*************** b2bbbaabe175be303181965daf230053  gcc/co
*** 4205,4212 ****
  b19c27e8a900f9eeb7d73e2bb4b8d313  gcc/config/i386/i386-rust.cc
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  7e925dbd61d7fe476ab7f718826d5ce0  gcc/config/i386/i386.cc
! 76d36c46700c68302dde0efc368c7ef8  gcc/config/i386/i386.h
! e8c1dd0c6139da9754234b6d00c21c4f  gcc/config/i386/i386.md
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--- 4205,4212 ----
  b19c27e8a900f9eeb7d73e2bb4b8d313  gcc/config/i386/i386-rust.cc
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! e7a05fc52c4e2695fe91e98acbccaad5  gcc/config/i386/i386.h
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*************** de4e89bc042c6bc7eb093bda5d33a266  gcc/co
*** 4269,4275 ****
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! 778821a1e3b401c74c6e531cad288029  gcc/config/i386/sse.md
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--- 4269,4275 ----
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! 6f18309c92312a94672bbb19b67a345f  gcc/config/i386/sse.md
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*************** bcefe099935dfbd7bc9b6d446d83949a  gcc/co
*** 5103,5111 ****
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! d139903a564018061688043567f8c198  gcc/config/rs6000/rs6000-builtin.cc
! dce39de8bb20b88ffeb8b2073101dcfe  gcc/config/rs6000/rs6000-builtins.def
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--- 5103,5111 ----
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*************** dce39de8bb20b88ffeb8b2073101dcfe  gcc/co
*** 5116,5130 ****
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! 9cac1be078f1b1cc7379bf75c3a74ba4  gcc/config/rs6000/rs6000-protos.h
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! b12290304c608ee478673c8dece8548e  gcc/config/rs6000/rs6000.cc
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--- 5116,5130 ----
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! bdd231712a9b96e04bdaaf1c8336e0fa  gcc/config/rs6000/rs6000-overload.def
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  533b1c41eb2f01d2e2f88b791b39979c  gcc/config/rs6000/rs6000-pcrel-opt.cc
! adbb131725969c4ea0811f86eeb9de8d  gcc/config/rs6000/rs6000-protos.h
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! 9bc4ad71426c3a19e4b5b9d689f54887  gcc/config/rs6000/rs6000.cc
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*************** ad1b62754d030b34f5ff67d2991b43b1  gcc/co
*** 5135,5141 ****
  10b358a1be6a0dae0450bff647690c8c  gcc/config/rs6000/si2vmx.h
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  a78086db7c3178a044593d53d3ae91c8  gcc/config/rs6000/spu2vmx.h
! 7b451b5476bf2c5f0f7cbcf6ed654e97  gcc/config/rs6000/sync.md
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  665ad5fb698deb6ee59b34e0b9f64c6d  gcc/config/rs6000/sysv4.opt.urls
--- 5135,5141 ----
  10b358a1be6a0dae0450bff647690c8c  gcc/config/rs6000/si2vmx.h
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! c2d8d466308f583ae9ab5b53b911a705  gcc/config/rs6000/sync.md
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*************** d7112093049d4abbc421609d032b7358  gcc/co
*** 5223,5231 ****
  6fdfe66fdde3f81b83dc16c27ac7df3f  gcc/config/s390/s390-opts.h
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  4bbcb1bde4546fee12249a01f76cb56e  gcc/config/s390/s390-protos.h
! 4cc3187327abfd8d4411757ee6d5ca64  gcc/config/s390/s390.cc
  f162b44703353c72956061efcbe580d7  gcc/config/s390/s390.h
! a71dab2465c50a816144f258baf600b7  gcc/config/s390/s390.md
  fa4475320c7a3767bf9accfa736efcc6  gcc/config/s390/s390.opt
  a70af895ec82511886ce63dc841e63e1  gcc/config/s390/s390.opt.urls
  b9ecea5f97b2e15b60d770050a07f0d1  gcc/config/s390/s390intrin.h
--- 5223,5231 ----
  6fdfe66fdde3f81b83dc16c27ac7df3f  gcc/config/s390/s390-opts.h
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! 30e1bcd02fc295eacca28b1a8fcc9f3d  gcc/config/s390/s390.cc
  f162b44703353c72956061efcbe580d7  gcc/config/s390/s390.h
! 5f305fca95d3dd8c8852c0d15dcbaca4  gcc/config/s390/s390.md
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  b9ecea5f97b2e15b60d770050a07f0d1  gcc/config/s390/s390intrin.h
*************** acdfc663791e4321372e79932070d05d  gcc/do
*** 5931,5937 ****
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*** 66021,66026 ****
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*** 69948,69954 ****
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*************** dc3bbe82f0ada40b2478603578aa8315  gcc/te
*** 70718,70724 ****
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*************** fb7ca982317505366c93c07e9b92b72a  gcc/te
*** 72657,72663 ****
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*** 72719,72725 ****
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*** 141225,141231 ****
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  ab943d9bc5490bc757c8302dfa9a2a91  libstdc++-v3/testsuite/27_io/filesystem/operations/relative.cc
--- 141239,141245 ----
  63be5a3c067bf8c58df4f2e1a10e1d34  libstdc++-v3/testsuite/27_io/filesystem/operations/is_empty.cc
  22c88037b133d9c9afac864b57d4f75a  libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc
  09e787d93c83c353884b09f81f023b10  libstdc++-v3/testsuite/27_io/filesystem/operations/permissions.cc
! 8c96b3b2206b4a258bec4e71bdf5c09d  libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc
  bf078a936e8205966cc6741bda17e038  libstdc++-v3/testsuite/27_io/filesystem/operations/proximate.cc
  b1bbe044bf2cc15fe9a6ecc95613510d  libstdc++-v3/testsuite/27_io/filesystem/operations/read_symlink.cc
  ab943d9bc5490bc757c8302dfa9a2a91  libstdc++-v3/testsuite/27_io/filesystem/operations/relative.cc
diff -Nrcpad gcc-15-20260626/gcc/ChangeLog gcc-15-20260703/gcc/ChangeLog
*** gcc-15-20260626/gcc/ChangeLog	Fri Jun 26 22:32:05 2026
--- gcc-15-20260703/gcc/ChangeLog	Fri Jul  3 22:32:05 2026
***************
*** 1,3 ****
--- 1,122 ----
+ 2026-07-01  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-26  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR target/125972
+ 	* config/s390/s390.cc (s390_rtx_costs): Deal with non-compare
+ 	conditions during costing.  Also fix some indentation.
+ 
+ 2026-07-01  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* tree-ssa-structalias.cc (set_uids_in_ptset): If ANYTHING is
+ 	present in the ESCAPED_RETURN solution, record that the global
+ 	solution has an escaped heap if FROM contains a heap variable.
+ 
+ 2026-07-01  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-06-30  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 		    Surya Kumari Jangala  <jskumari@linux.ibm.com>
+ 
+ 	* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Add logic to
+ 	handle __builtin_ppc_atomic_cas_local.
+ 	* config/rs6000/rs6000-builtins.def: New builtins for
+ 	__builtin_ppc_atomic_cas_local with types.
+ 	* config/rs6000/rs6000-c.cc (altivec_build_resolved_builtin): Handle
+ 	builtins with up to 6 arguments.
+ 	* config/rs6000/rs6000-overload.def: Overload builtin for signed/unsiged
+ 	char, short, int, long, __int128.
+ 	* config/rs6000/rs6000-protos.h (rs6000_expand_atomic_compare_and_swap): Add
+ 	additional parameter 'local' to the prototype.
+ 	* config/rs6000/rs6000.cc (emit_load_locked): Add new parameter. Pass new
+ 	parameter to generate load-locked instruction.
+ 	(rs6000_expand_atomic_compare_and_swap): Add new parameter. Call
+ 	emit_load_locked() with additional parameter value of EH bit.
+ 	(rs6000_expand_atomic_exchange): Pass EH value 0 to emit_load_locked().
+ 	(rs6000_expand_atomic_op): Likewise.
+ 	* config/rs6000/sync.md (load_locked<mode>): Add new operand in RTL template.
+ 	Specify EH bit in the larx instruction.
+ 	(load_locked<QHI:mode>_si): Likewise.
+ 	(load_lockedpti): Likewise.
+ 	(load_lockedti): Add new operand in RTL template. Pass EH bit to
+ 	gen_load_lockedpti().
+ 	(atomic_compare_and_swap<mode>): Pass new parameter 'false' to
+ 	rs6000_expand_atomic_compare_and_swap.
+ 	(atomic_compare_and_swap_local<mode>): New define_expand.
+ 	* doc/extend.texi: Add documentation for new builtin.
+ 
+ 2026-07-01  Haochen Jiang  <haochen.jiang@intel.com>
+ 
+ 	* config/i386/i386.h (PTA_DIAMONDRAPIDS): Remove PTA_AMX_TF32.
+ 	* doc/invoke.texi: Correct documentation.
+ 
+ 2026-06-30  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-12  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR rtl-optimization/125173
+ 	* ira.cc (combine_and_move_insns): Allow multiple uses within
+ 	an insn.
+ 
+ 2026-06-30  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2026-04-22  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/124908
+ 	* config/aarch64/aarch64-sve-builtins-base.cc
+ 	(svld1rq_impl::fold): When the SVE vector length equals the
+ 	quadword width, emit VIEW_CONVERT_EXPR instead of VEC_PERM_EXPR.
+ 
+ 2026-06-29  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	Backported from master:
+ 	2026-06-23  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	PR target/125818
+ 	* config/aarch64/aarch64-sve-builtins-base.cc (svset_impl::fold): Fix
+ 	unsharing to ensure the returned stmt has the exact same lhs as the
+ 	original.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125469
+ 	* config/i386/i386.md (*add<mode>_1<nf_name>): Revert 2026-05-28
+ 	changes.
+ 	(define_split from *add<mode>_1_nf to *lea<mode>): Set INSN_CODE
+ 	to -1 if <LEAMODE> and <MODE> are the same.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-28  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125469
+ 	* config/i386/i386.md (*add<mode>_1<nf_name>): Don't return "#" for
+ 	the lea non-TARGET_APX_NDD case, instead emit a lea directly.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125992
+ 	* config/s390/s390.md (*brx_stage1_<GPR:mode>): Add CC_REGNUM clobber.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125611
+ 	* config/i386/sse.md (<ssse3_avx2>_pmulhrsw<mode>3, smulhrs<mode>3):
+ 	Use vector_operand instead of nonimmediate_operand.
+ 
  2026-06-22  Robin Dapp  <rdapp.gcc@gmail.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260626/gcc/DATESTAMP gcc-15-20260703/gcc/DATESTAMP
*** gcc-15-20260626/gcc/DATESTAMP	Fri Jun 26 22:32:05 2026
--- gcc-15-20260703/gcc/DATESTAMP	Fri Jul  3 22:32:05 2026
***************
*** 1 ****
! 20260626
--- 1 ----
! 20260703
diff -Nrcpad gcc-15-20260626/gcc/ada/ChangeLog gcc-15-20260703/gcc/ada/ChangeLog
*** gcc-15-20260626/gcc/ada/ChangeLog	Fri Jun 26 22:32:05 2026
--- gcc-15-20260703/gcc/ada/ChangeLog	Fri Jul  3 22:32:05 2026
***************
*** 1,3 ****
--- 1,13 ----
+ 2026-06-29  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* exp_util.ads (Find_Optional_Prim_Op): Add Controlled_Op parameter
+ 	defaulting to False.
+ 	* exp_util.adb (Find_Optional_Prim_Op): Likewise.  When it is set to
+ 	True, test whether the primitive has the signature of the controlled
+ 	primitives.
+ 	* sem_ch13.adb (Resolve_Finalization_Procedure): Reset Is_Overloaded
+ 	once an interpretation has been selected among the set.
+ 
  2026-06-12  Release Manager
  
  	* GCC 15.3.0 released.
diff -Nrcpad gcc-15-20260626/gcc/ada/exp_util.adb gcc-15-20260703/gcc/ada/exp_util.adb
*** gcc-15-20260626/gcc/ada/exp_util.adb	Fri Jun 26 22:32:05 2026
--- gcc-15-20260703/gcc/ada/exp_util.adb	Fri Jul  3 22:32:05 2026
*************** package body Exp_Util is
*** 6124,6130 ****
           return Empty;
        end if;
  
!       return Find_Optional_Prim_Op (T, Op_Name);
     end Find_Controlled_Prim_Op;
  
     ------------------------
--- 6124,6130 ----
           return Empty;
        end if;
  
!       return Find_Optional_Prim_Op (T, Op_Name, Controlled_Op => True);
     end Find_Controlled_Prim_Op;
  
     ------------------------
*************** package body Exp_Util is
*** 6631,6641 ****
     ---------------------------
  
     function Find_Optional_Prim_Op
!      (T : Entity_Id; Name : Name_Id) return Entity_Id
     is
        Prim : Elmt_Id;
        Typ  : Entity_Id := T;
-       Op   : Entity_Id;
  
     begin
        if Is_Class_Wide_Type (Typ) then
--- 6631,6643 ----
     ---------------------------
  
     function Find_Optional_Prim_Op
!      (T             : Entity_Id;
!       Name          : Name_Id;
!       Controlled_Op : Boolean := False) return Entity_Id
     is
+       Op   : Entity_Id;
        Prim : Elmt_Id;
        Typ  : Entity_Id := T;
  
     begin
        if Is_Class_Wide_Type (Typ) then
*************** package body Exp_Util is
*** 6657,6670 ****
           Op := Node (Prim);
  
           --  We can retrieve primitive operations by name if it is an internal
!          --  name. For equality we must check that both of its operands have
!          --  the same type, to avoid confusion with user-defined equalities
!          --  than may have a asymmetric signature.
  
           exit when Chars (Op) = Name
             and then
               (Name /= Name_Op_Eq
!                or else Etype (First_Formal (Op)) = Etype (Last_Formal (Op)));
  
           Next_Elmt (Prim);
        end loop;
--- 6659,6681 ----
           Op := Node (Prim);
  
           --  We can retrieve primitive operations by name if it is an internal
!          --  name. For equality, we must check that both of its operands have
!          --  the same type, to avoid confusion with user-defined equalities,
!          --  which may have an asymmetric signature. For controlled operations,
!          --  we check that the primitive is a procedure with a single In Out
!          --  parameter of a non-access type.
  
           exit when Chars (Op) = Name
             and then
               (Name /= Name_Op_Eq
!                or else Etype (First_Formal (Op)) = Etype (Last_Formal (Op)))
!            and then
!              (not Controlled_Op
!                or else
!                  (Ekind (Op) = E_Procedure
!                    and then Ekind (First_Formal (Op)) = E_In_Out_Parameter
!                    and then not Is_Access_Type (Etype (First_Formal (Op)))
!                    and then No (Next_Formal (First_Formal (Op)))));
  
           Next_Elmt (Prim);
        end loop;
diff -Nrcpad gcc-15-20260626/gcc/ada/exp_util.ads gcc-15-20260703/gcc/ada/exp_util.ads
*** gcc-15-20260626/gcc/ada/exp_util.ads	Fri Jun 26 22:32:05 2026
--- gcc-15-20260703/gcc/ada/exp_util.ads	Fri Jul  3 22:32:05 2026
*************** package Exp_Util is
*** 645,651 ****
     --  and returns Empty if not found.
  
     function Find_Optional_Prim_Op
!      (T : Entity_Id; Name : Name_Id) return Entity_Id;
     function Find_Optional_Prim_Op
       (T    : Entity_Id;
        Name : TSS_Name_Type) return Entity_Id;
--- 645,657 ----
     --  and returns Empty if not found.
  
     function Find_Optional_Prim_Op
!      (T             : Entity_Id;
!       Name          : Name_Id;
!       Controlled_Op : Boolean := False) return Entity_Id;
!    --  Same as Find_Prim_Op but, if Controlled_Op is True, returns a primitive
!    --  only if it has the signature of the three primitives of controlled types
!    --  Initialize/Adjust/Finalize, and returns Empty if not found.
! 
     function Find_Optional_Prim_Op
       (T    : Entity_Id;
        Name : TSS_Name_Type) return Entity_Id;
diff -Nrcpad gcc-15-20260626/gcc/ada/sem_ch13.adb gcc-15-20260703/gcc/ada/sem_ch13.adb
*** gcc-15-20260626/gcc/ada/sem_ch13.adb	Fri Jun 26 22:32:06 2026
--- gcc-15-20260703/gcc/ada/sem_ch13.adb	Fri Jul  3 22:32:06 2026
*************** package body Sem_Ch13 is
*** 16930,16935 ****
--- 16930,16936 ----
              while Present (It.Typ) loop
                 if Is_Finalizable_Primitive (It.Nam) then
                    Set_Entity (N, It.Nam);
+                   Set_Is_Overloaded (N, False);
                    return;
                 end if;
  
diff -Nrcpad gcc-15-20260626/gcc/config/aarch64/aarch64-sve-builtins-base.cc gcc-15-20260703/gcc/config/aarch64/aarch64-sve-builtins-base.cc
*** gcc-15-20260626/gcc/config/aarch64/aarch64-sve-builtins-base.cc	Fri Jun 26 22:32:06 2026
--- gcc-15-20260703/gcc/config/aarch64/aarch64-sve-builtins-base.cc	Fri Jul  3 22:32:06 2026
*************** public:
*** 1830,1835 ****
--- 1830,1849 ----
  	gimple_seq_add_stmt_without_update (&stmts, mem_ref_stmt);
  
  	int source_nelts = TYPE_VECTOR_SUBPARTS (access_type).to_constant ();
+ 
+ 	/* When the SVE vector has the same number of elements as the
+ 	   128-bit quadword (i.e. VL == 128), the load fills the entire
+ 	   register and no replication is needed.  Just convert the
+ 	   loaded value from the Advanced SIMD type to the SVE type.  */
+ 	if (known_eq (lhs_len, (unsigned int) source_nelts))
+ 	  {
+ 	    gimple *g
+ 	      = gimple_build_assign (lhs, build1 (VIEW_CONVERT_EXPR,
+ 						  lhs_type, mem_ref_lhs));
+ 	    gimple_seq_add_stmt_without_update (&stmts, g);
+ 	    gsi_replace_with_seq_vops (f.gsi, stmts);
+ 	    return g;
+ 	  }
  	vec_perm_builder sel (lhs_len, source_nelts, 1);
  	for (int i = 0; i < source_nelts; i++)
  	  sel.quick_push (i);
*************** public:
*** 2937,2948 ****
         The fold routines expect the replacement statement to have the
         same lhs as the original call, so return the copy statement
         rather than the field update.  */
!     gassign *copy = gimple_build_assign (unshare_expr (f.lhs), rhs_tuple);
  
      /* Get a reference to the individual vector.  */
      tree field = tuple_type_field (TREE_TYPE (f.lhs));
      tree lhs_array = build3 (COMPONENT_REF, TREE_TYPE (field),
! 			     f.lhs, field, NULL_TREE);
      tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector),
  			      lhs_array, index, NULL_TREE, NULL_TREE);
      gassign *update = gimple_build_assign (lhs_vector, rhs_vector);
--- 2951,2962 ----
         The fold routines expect the replacement statement to have the
         same lhs as the original call, so return the copy statement
         rather than the field update.  */
!     gassign *copy = gimple_build_assign (f.lhs, rhs_tuple);
  
      /* Get a reference to the individual vector.  */
      tree field = tuple_type_field (TREE_TYPE (f.lhs));
      tree lhs_array = build3 (COMPONENT_REF, TREE_TYPE (field),
! 			     unshare_expr (f.lhs), field, NULL_TREE);
      tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector),
  			      lhs_array, index, NULL_TREE, NULL_TREE);
      gassign *update = gimple_build_assign (lhs_vector, rhs_vector);
diff -Nrcpad gcc-15-20260626/gcc/config/i386/i386.h gcc-15-20260703/gcc/config/i386/i386.h
*** gcc-15-20260626/gcc/config/i386/i386.h	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/i386/i386.h	Fri Jul  3 22:32:07 2026
*************** constexpr wide_int_bitmask PTA_DIAMONDRA
*** 2458,2465 ****
    | PTA_AMX_FP16 | PTA_PREFETCHI | PTA_AMX_COMPLEX | PTA_AVX10_1_256
    | PTA_AVX10_1 | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16
    | PTA_AVXVNNIINT8 | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4
!   | PTA_AVX10_2 | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32
!   | PTA_MOVRS | PTA_AMX_MOVRS;
  
  constexpr wide_int_bitmask PTA_BDVER1 = PTA_64BIT | PTA_MMX | PTA_SSE
    | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3
--- 2458,2465 ----
    | PTA_AMX_FP16 | PTA_PREFETCHI | PTA_AMX_COMPLEX | PTA_AVX10_1_256
    | PTA_AVX10_1 | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16
    | PTA_AVXVNNIINT8 | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4
!   | PTA_AVX10_2 | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_MOVRS
!   | PTA_AMX_MOVRS;
  
  constexpr wide_int_bitmask PTA_BDVER1 = PTA_64BIT | PTA_MMX | PTA_SSE
    | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3
diff -Nrcpad gcc-15-20260626/gcc/config/i386/i386.md gcc-15-20260703/gcc/config/i386/i386.md
*** gcc-15-20260626/gcc/config/i386/i386.md	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/i386/i386.md	Fri Jul  3 22:32:07 2026
***************
*** 7160,7165 ****
--- 7160,7170 ----
        operands[1] = gen_lowpart (<LEAMODE>mode, operands[1]);
        operands[2] = gen_lowpart (<LEAMODE>mode, operands[2]);
      }
+   else
+     /* *lea<mode> and *add<mode>_1_nf have the same pattern, try_split
+        refuses to split an insn into itself, so just request
+        a new recog which will match *lea<mode> which comes first.  */
+     INSN_CODE (curr_insn) = -1;
  })
  
  ;; Convert add to the lea pattern to avoid flags dependency.
diff -Nrcpad gcc-15-20260626/gcc/config/i386/sse.md gcc-15-20260703/gcc/config/i386/sse.md
*** gcc-15-20260626/gcc/config/i386/sse.md	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/i386/sse.md	Fri Jul  3 22:32:07 2026
***************
*** 23071,23079 ****
  	      (lshiftrt:<ssedoublemode>
  		(mult:<ssedoublemode>
  		  (sign_extend:<ssedoublemode>
! 		    (match_operand:PMULHRSW 1 "nonimmediate_operand"))
  		  (sign_extend:<ssedoublemode>
! 		    (match_operand:PMULHRSW 2 "nonimmediate_operand")))
  		(const_int 14))
  	      (match_dup 3))
  	    (const_int 1))))]
--- 23071,23079 ----
  	      (lshiftrt:<ssedoublemode>
  		(mult:<ssedoublemode>
  		  (sign_extend:<ssedoublemode>
! 		    (match_operand:PMULHRSW 1 "vector_operand"))
  		  (sign_extend:<ssedoublemode>
! 		    (match_operand:PMULHRSW 2 "vector_operand")))
  		(const_int 14))
  	      (match_dup 3))
  	    (const_int 1))))]
***************
*** 23091,23099 ****
  	      (lshiftrt:<ssedoublemode>
  		(mult:<ssedoublemode>
  		  (sign_extend:<ssedoublemode>
! 		    (match_operand:VI2_AVX2_AVX512BW 1 "nonimmediate_operand"))
  		  (sign_extend:<ssedoublemode>
! 		    (match_operand:VI2_AVX2_AVX512BW 2 "nonimmediate_operand")))
  		(const_int 14))
  	      (match_dup 3))
  	    (const_int 1))))]
--- 23091,23099 ----
  	      (lshiftrt:<ssedoublemode>
  		(mult:<ssedoublemode>
  		  (sign_extend:<ssedoublemode>
! 		    (match_operand:VI2_AVX2_AVX512BW 1 "vector_operand"))
  		  (sign_extend:<ssedoublemode>
! 		    (match_operand:VI2_AVX2_AVX512BW 2 "vector_operand")))
  		(const_int 14))
  	      (match_dup 3))
  	    (const_int 1))))]
diff -Nrcpad gcc-15-20260626/gcc/config/rs6000/rs6000-builtin.cc gcc-15-20260703/gcc/config/rs6000/rs6000-builtin.cc
*** gcc-15-20260626/gcc/config/rs6000/rs6000-builtin.cc	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/rs6000/rs6000-builtin.cc	Fri Jul  3 22:32:07 2026
*************** rs6000_expand_builtin (tree exp, rtx tar
*** 3284,3289 ****
--- 3284,3395 ----
        return expand_call (exp, target, ignore);
      }
  
+   if (fcode == RS6000_BIF_PPC_ATOMIC_CAS_QI
+       || fcode == RS6000_BIF_PPC_ATOMIC_CAS_HI
+       || fcode == RS6000_BIF_PPC_ATOMIC_CAS_SI
+       || fcode == RS6000_BIF_PPC_ATOMIC_CAS_DI
+       || fcode == RS6000_BIF_PPC_ATOMIC_CAS_TI)
+     {
+       machine_mode mode; // Get mode based on BIF ID (QImode, SImode, etc.)
+ 
+       switch (fcode)
+ 	{
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_QI:
+ 	  mode = QImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localqi;
+ 	  break;
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_HI:
+ 	  mode = HImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localhi;
+ 	  break;
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_SI:
+ 	  mode = SImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localsi;
+ 	  break;
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_DI:
+ 	  mode = DImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localdi;
+ 	  break;
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_TI:
+ 	  mode = TImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localti;
+ 	  break;
+ 	default:
+ 	  gcc_unreachable ();
+ 	}
+ 
+       // For arg 0 (ptr to data)
+       rtx ptr = expand_expr (CALL_EXPR_ARG (exp, 0), NULL_RTX, Pmode,
+ 			     EXPAND_SUM);
+       ptr = convert_memory_address (Pmode, ptr);
+       rtx mem = gen_rtx_MEM (mode, ptr);
+ 
+       // For arg 1 (expected ptr)
+       rtx exp_ptr = expand_expr (CALL_EXPR_ARG (exp, 1), NULL_RTX, Pmode,
+ 				 EXPAND_SUM);
+       exp_ptr = convert_memory_address (Pmode, exp_ptr);
+       rtx expected_val = gen_reg_rtx (mode);
+       emit_move_insn (expected_val, gen_rtx_MEM (mode, exp_ptr));
+ 
+       // For arg 2 (desired ptr)
+       rtx desired_ptr = expand_expr (CALL_EXPR_ARG (exp, 2), NULL_RTX, Pmode,
+ 				     EXPAND_SUM);
+       desired_ptr = convert_memory_address (Pmode, desired_ptr);
+       rtx desired_val = gen_reg_rtx (mode);
+       emit_move_insn (desired_val, gen_rtx_MEM (mode, desired_ptr));
+ 
+       // Args 3, 4, 5: weak, succ, fail (constants)
+       rtx weak = expand_normal (CALL_EXPR_ARG (exp, 3));
+       rtx succ = expand_normal (CALL_EXPR_ARG (exp, 4));
+       rtx fail = expand_normal (CALL_EXPR_ARG (exp, 5));
+ 
+       // 0: Boolean return (Output)
+       struct expand_operand ops[8];
+       create_output_operand (&ops[0], target, SImode);
+ 
+       // 1: Old value return (Output)
+       rtx old_val = gen_reg_rtx (mode);
+       create_output_operand (&ops[1], old_val, mode);
+ 
+       // 2: The Memory (Fixed/Input - it's a MEM rtx)
+       // We use create_fixed_operand because it's a specific MEM location
+       create_fixed_operand (&ops[2], mem);
+ 
+       // 3: Expected Value (Input)
+       create_input_operand (&ops[3], expected_val, mode);
+ 
+       // 4: Desired Value (Input)
+       create_input_operand (&ops[4], desired_val, mode);
+ 
+       // 5, 6, 7: Weak, Success, Failure (Immediate/Constants)
+       create_input_operand (&ops[5], weak, SImode);
+       create_input_operand (&ops[6], succ, SImode);
+       create_input_operand (&ops[7], fail, SImode);
+ 
+       // Now call expand_insn with the ops array
+       if (!maybe_expand_insn (icode, 8, ops))
+ 	error ("invalid arguments to builtin");
+ 
+       // Create a label for the end of the function.
+       rtx done_label = gen_label_rtx ();
+ 
+       /* Standard Semantics: Update 'expected' ONLY on failure.
+ 	 If target (the boolean result) is NOT 0, the CAS succeeded.
+ 	 In the case of success, we jump straight to the end.  */
+ 
+       // If target != 0 (Success), skip the store.
+       emit_cmp_and_jump_insns (target, const0_rtx, NE, NULL_RTX,
+ 			       SImode, 1, done_label);
+ 
+       // FAILURE PATH: This code runs only if target == 0.
+       rtx expected_mem = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, exp_ptr));
+       emit_move_insn (expected_mem, old_val);
+ 
+       emit_label (done_label);
+ 
+       return target;
+     }
+ 
    if (bif_is_nosoft (*bifaddr)
        && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
      {
diff -Nrcpad gcc-15-20260626/gcc/config/rs6000/rs6000-builtins.def gcc-15-20260703/gcc/config/rs6000/rs6000-builtins.def
*** gcc-15-20260626/gcc/config/rs6000/rs6000-builtins.def	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/rs6000/rs6000-builtins.def	Fri Jul  3 22:32:07 2026
***************
*** 246,251 ****
--- 246,268 ----
    const double __builtin_unpack_longdouble (long double, const int<1>);
      UNPACK_TF unpacktf {ibmld}
  
+ ; Builtins for ppc specific atomic compare exchange
+   bool __builtin_ppc_atomic_cas_local_qi (char *, char *, char *, const int, \
+ 					  const int, const int);
+     PPC_ATOMIC_CAS_QI nothing {}
+   bool __builtin_ppc_atomic_cas_local_hi (short *, short *, short *, \
+ 					  const int, const int, const int);
+     PPC_ATOMIC_CAS_HI nothing {}
+   bool __builtin_ppc_atomic_cas_local_si (int *, int *, int *, const int, \
+ 					  const int, const int);
+     PPC_ATOMIC_CAS_SI nothing {}
+   bool __builtin_ppc_atomic_cas_local_di (long long *, long long *, \
+ 					  long long *, const int, const int, \
+ 					  const int);
+     PPC_ATOMIC_CAS_DI nothing {}
+   bool __builtin_ppc_atomic_cas_local_ti (__int128 *, __int128 *, __int128 *, \
+ 					  const int, const int, const int);
+     PPC_ATOMIC_CAS_TI nothing {}
  
  ; Builtins that have been around just about forever, but not quite.
  [power5]
diff -Nrcpad gcc-15-20260626/gcc/config/rs6000/rs6000-c.cc gcc-15-20260703/gcc/config/rs6000/rs6000-c.cc
*** gcc-15-20260626/gcc/config/rs6000/rs6000-c.cc	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/rs6000/rs6000-c.cc	Fri Jul  3 22:32:07 2026
*************** altivec_build_resolved_builtin (tree *ar
*** 927,933 ****
  
    /* If the number of arguments to an overloaded function increases,
       we must expand this switch.  */
!   gcc_assert (MAX_OVLD_ARGS <= 4);
  
    tree call;
    switch (n)
--- 927,933 ----
  
    /* If the number of arguments to an overloaded function increases,
       we must expand this switch.  */
!   gcc_assert (MAX_OVLD_ARGS <= 6);
  
    tree call;
    switch (n)
*************** altivec_build_resolved_builtin (tree *ar
*** 947,952 ****
--- 947,956 ----
      case 4:
        call = build_call_expr (fndecl, 4, args[0], args[1], args[2], args[3]);
        break;
+     case 6:
+       call = build_call_expr (fndecl, 6, args[0], args[1], args[2], args[3],
+ 			      args[4], args[5]);
+       break;
      default:
        gcc_unreachable ();
      }
*************** find_instance (bool *unsupported_builtin
*** 1708,1718 ****
  
  tree
  altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
! 				    void *passed_arglist, bool)
  {
    rs6000_gen_builtins fcode
      = (rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl);
  
    /* Return immediately if this isn't an overload.  */
    if (fcode <= RS6000_OVLD_NONE)
      return NULL_TREE;
--- 1712,1833 ----
  
  tree
  altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
! 				    void *passed_arglist, bool complain)
  {
    rs6000_gen_builtins fcode
      = (rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl);
  
+   /* Handle __builtin_ppc_atomic_cas_local before standard overload
+      processing.  */
+   if (fcode == RS6000_OVLD_PPC_ATOMIC_CAS)
+     {
+       vec<tree, va_gc> *arglist
+ 	= static_cast<vec<tree, va_gc> *> (passed_arglist);
+ 
+       /* Expected: (void *ptr, void *expected, void *desired,
+       bool weak, int success_order, int failure_order).  */
+       if (vec_safe_length (arglist) != 6)
+ 	{
+ 	  if (complain)
+ 	    error_at (loc, "%qE requires 6 arguments", fndecl);
+ 	  return error_mark_node;
+ 	}
+ 
+       /* Get the first argument to determine the actual type.  */
+       tree arg0 = (*arglist)[0];
+       tree type0 = TREE_TYPE (arg0);
+ 
+       /* Must be a pointer.  */
+       if (!POINTER_TYPE_P (type0))
+ 	{
+ 	  if (complain)
+ 	    error_at (loc, "first argument to %qE must be a pointer", fndecl);
+ 	  return error_mark_node;
+ 	}
+ 
+       /* Get the pointee type.  */
+       tree pointee_type = TREE_TYPE (type0);
+ 
+       /* Must be a complete type.  */
+       if (!COMPLETE_TYPE_P (pointee_type))
+ 	{
+ 	  if (complain)
+ 	    error_at (loc, "first argument to %qE must point to a complete"
+ 		      " type", fndecl);
+ 	  return error_mark_node;
+ 	}
+ 
+       /* Get size in bytes.  */
+       tree size_tree = TYPE_SIZE_UNIT (pointee_type);
+       if (!tree_fits_uhwi_p (size_tree))
+ 	{
+ 	  if (complain)
+ 	    error_at (loc, "type size must be constant");
+ 	  return error_mark_node;
+ 	}
+ 
+       unsigned HOST_WIDE_INT size = tree_to_uhwi (size_tree);
+ 
+       /* Determine which size-specific builtin to use.  */
+       rs6000_gen_builtins target_fcode;
+       tree int_type;
+ 
+       switch (size)
+ 	{
+ 	case 1:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_QI;
+ 	  int_type = unsigned_char_type_node;
+ 	  break;
+ 	case 2:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_HI;
+ 	  int_type = short_unsigned_type_node;
+ 	  break;
+ 	case 4:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_SI;
+ 	  int_type = unsigned_intSI_type_node;
+ 	  break;
+ 	case 8:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_DI;
+ 	  int_type = long_long_unsigned_type_node;
+ 	  break;
+ 	case 16:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_TI;
+ 	  int_type = unsigned_intTI_type_node;
+ 	  break;
+ 	default:
+ 	  if (complain)
+ 	    error_at (loc, "size %wu not supported for %qE "
+ 		      "(must be 1, 2, 4, 8, or 16 bytes)", size, fndecl);
+ 	  return error_mark_node;
+ 	}
+ 
+       /* Create pointer type to the appropriate integer type.  */
+       tree int_ptr_type = build_pointer_type (int_type);
+ 
+       /* Cast the three pointer arguments to the appropriate integer
+       pointer type.  */
+       tree new_arg0 = build1 (VIEW_CONVERT_EXPR, int_ptr_type, (*arglist)[0]);
+       tree new_arg1 = build1 (VIEW_CONVERT_EXPR, int_ptr_type, (*arglist)[1]);
+       tree new_arg2 = build1 (VIEW_CONVERT_EXPR, int_ptr_type, (*arglist)[2]);
+ 
+       /* Build new argument list with casted pointers.  */
+       vec<tree, va_gc> *new_arglist;
+       vec_alloc (new_arglist, 6);
+       new_arglist->quick_push (new_arg0);
+       new_arglist->quick_push (new_arg1);
+       new_arglist->quick_push (new_arg2);
+       new_arglist->quick_push ((*arglist)[3]);  /* weak (bool).  */
+       new_arglist->quick_push ((*arglist)[4]);  /* success_memorder.  */
+       new_arglist->quick_push ((*arglist)[5]);  /* failure_memorder.  */
+ 
+       /* Get the target builtin function.  */
+       tree new_fndecl = rs6000_builtin_decls[target_fcode];
+ 
+       /* Build and return the function call.  */
+       return build_function_call_vec (loc, vNULL, new_fndecl, new_arglist,
+ 				      NULL, fndecl);
+     }
+ 
    /* Return immediately if this isn't an overload.  */
    if (fcode <= RS6000_OVLD_NONE)
      return NULL_TREE;
diff -Nrcpad gcc-15-20260626/gcc/config/rs6000/rs6000-overload.def gcc-15-20260703/gcc/config/rs6000/rs6000-overload.def
*** gcc-15-20260626/gcc/config/rs6000/rs6000-overload.def	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/rs6000/rs6000-overload.def	Fri Jul  3 22:32:07 2026
***************
*** 79,84 ****
--- 79,92 ----
  ; a semicolon are also treated as blank lines.
  
  
+ ; The following function is not overloaded, but is internally substituted by
+ ; __builtin_ppc_atomic_cas_local_{qi,hi,si,di,ti} based on the first 3
+ ; arguments.
+ [PPC_ATOMIC_CAS, SKIP, __builtin_ppc_atomic_cas_local]
+   bool __builtin_ppc_atomic_cas_local (void *, void *, void *, const int, \
+ 				       const int, const int);
+     PPC_ATOMIC_CAS_QI PPC_ATOMIC_CAS_FAKERY
+ 
  [BCDADD, __builtin_bcdadd, __builtin_vec_bcdadd]
    vsq __builtin_vec_bcdadd (vsq, vsq, const int);
      BCDADD_V1TI
diff -Nrcpad gcc-15-20260626/gcc/config/rs6000/rs6000-protos.h gcc-15-20260703/gcc/config/rs6000/rs6000-protos.h
*** gcc-15-20260626/gcc/config/rs6000/rs6000-protos.h	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/rs6000/rs6000-protos.h	Fri Jul  3 22:32:07 2026
*************** extern bool rs6000_emit_set_const (rtx,
*** 127,133 ****
  extern bool rs6000_emit_cmove (rtx, rtx, rtx, rtx);
  extern bool rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
  extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
! extern void rs6000_expand_atomic_compare_and_swap (rtx op[]);
  extern rtx swap_endian_selector_for_mode (machine_mode mode);
  
  extern void rs6000_expand_atomic_exchange (rtx op[]);
--- 127,133 ----
  extern bool rs6000_emit_cmove (rtx, rtx, rtx, rtx);
  extern bool rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
  extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
! extern void rs6000_expand_atomic_compare_and_swap (rtx op[], bool local);
  extern rtx swap_endian_selector_for_mode (machine_mode mode);
  
  extern void rs6000_expand_atomic_exchange (rtx op[]);
diff -Nrcpad gcc-15-20260626/gcc/config/rs6000/rs6000.cc gcc-15-20260703/gcc/config/rs6000/rs6000.cc
*** gcc-15-20260626/gcc/config/rs6000/rs6000.cc	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/rs6000/rs6000.cc	Fri Jul  3 22:32:07 2026
*************** emit_unlikely_jump (rtx cond, rtx label)
*** 16735,16746 ****
  
  /* A subroutine of the atomic operation splitters.  Emit a load-locked
     instruction in MODE.  For QI/HImode, possibly use a pattern than includes
!    the zero_extend operation.  */
  
  static void
! emit_load_locked (machine_mode mode, rtx reg, rtx mem)
  {
!   rtx (*fn) (rtx, rtx) = NULL;
  
    switch (mode)
      {
--- 16735,16747 ----
  
  /* A subroutine of the atomic operation splitters.  Emit a load-locked
     instruction in MODE.  For QI/HImode, possibly use a pattern than includes
!    the zero_extend operation.  LOCAL indicates the EH bit value for the
!    load-locked instruction.  */
  
  static void
! emit_load_locked (machine_mode mode, rtx reg, rtx mem, rtx local)
  {
!   rtx (*fn) (rtx, rtx, rtx) = NULL;
  
    switch (mode)
      {
*************** emit_load_locked (machine_mode mode, rtx
*** 16767,16773 ****
      default:
        gcc_unreachable ();
      }
!   emit_insn (fn (reg, mem));
  }
  
  /* A subroutine of the atomic operation splitters.  Emit a store-conditional
--- 16768,16774 ----
      default:
        gcc_unreachable ();
      }
!   emit_insn (fn (reg, mem, local));
  }
  
  /* A subroutine of the atomic operation splitters.  Emit a store-conditional
*************** rs6000_finish_atomic_subword (rtx narrow
*** 16937,16943 ****
  /* Expand an atomic compare and swap operation.  */
  
  void
! rs6000_expand_atomic_compare_and_swap (rtx operands[])
  {
    rtx boolval, retval, mem, oldval, newval, cond;
    rtx label1, label2, x, mask, shift;
--- 16938,16944 ----
  /* Expand an atomic compare and swap operation.  */
  
  void
! rs6000_expand_atomic_compare_and_swap (rtx operands[], bool local)
  {
    rtx boolval, retval, mem, oldval, newval, cond;
    rtx label1, label2, x, mask, shift;
*************** rs6000_expand_atomic_compare_and_swap (r
*** 17000,17006 ****
      }
    label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
  
!   emit_load_locked (mode, retval, mem);
  
    x = retval;
    if (mask)
--- 17001,17007 ----
      }
    label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
  
!   emit_load_locked (mode, retval, mem, local ? const1_rtx : const0_rtx);
  
    x = retval;
    if (mask)
*************** rs6000_expand_atomic_exchange (rtx opera
*** 17098,17104 ****
    label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
    emit_label (XEXP (label, 0));
  
!   emit_load_locked (mode, retval, mem);
  
    x = val;
    if (mask)
--- 17099,17105 ----
    label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
    emit_label (XEXP (label, 0));
  
!   emit_load_locked (mode, retval, mem, const0_rtx);
  
    x = val;
    if (mask)
*************** rs6000_expand_atomic_op (enum rtx_code c
*** 17203,17209 ****
    if (before == NULL_RTX)
      before = gen_reg_rtx (mode);
  
!   emit_load_locked (mode, before, mem);
  
    if (code == NOT)
      {
--- 17204,17210 ----
    if (before == NULL_RTX)
      before = gen_reg_rtx (mode);
  
!   emit_load_locked (mode, before, mem, const0_rtx);
  
    if (code == NOT)
      {
diff -Nrcpad gcc-15-20260626/gcc/config/rs6000/sync.md gcc-15-20260703/gcc/config/rs6000/sync.md
*** gcc-15-20260626/gcc/config/rs6000/sync.md	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/rs6000/sync.md	Fri Jul  3 22:32:07 2026
***************
*** 278,294 ****
  (define_insn "load_locked<mode>"
    [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")
  	(unspec_volatile:ATOMIC
!          [(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))]
    ""
!   "<larx> %0,%y1"
    [(set_attr "type" "load_l")])
  
  (define_insn "load_locked<QHI:mode>_si"
    [(set (match_operand:SI 0 "int_reg_operand" "=r")
  	(unspec_volatile:SI
! 	  [(match_operand:QHI 1 "memory_operand" "Z")] UNSPECV_LL))]
    "TARGET_SYNC_HI_QI"
!   "<QHI:larx> %0,%y1"
    [(set_attr "type" "load_l")])
  
  ;; Use PTImode to get even/odd register pairs.
--- 278,296 ----
  (define_insn "load_locked<mode>"
    [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")
  	(unspec_volatile:ATOMIC
! 	  [(match_operand:ATOMIC 1 "memory_operand" "Z")
! 	   (match_operand:QI 2 "u1bit_cint_operand" "n")] UNSPECV_LL))]
    ""
!   "<larx> %0,%y1,%2"
    [(set_attr "type" "load_l")])
  
  (define_insn "load_locked<QHI:mode>_si"
    [(set (match_operand:SI 0 "int_reg_operand" "=r")
  	(unspec_volatile:SI
! 	  [(match_operand:QHI 1 "memory_operand" "Z")
! 	   (match_operand:QI 2 "u1bit_cint_operand" "n")] UNSPECV_LL))]
    "TARGET_SYNC_HI_QI"
!   "<QHI:larx> %0,%y1,%2"
    [(set_attr "type" "load_l")])
  
  ;; Use PTImode to get even/odd register pairs.
***************
*** 302,308 ****
  
  (define_expand "load_lockedti"
    [(use (match_operand:TI 0 "quad_int_reg_operand"))
!    (use (match_operand:TI 1 "memory_operand"))]
    "TARGET_SYNC_TI"
  {
    rtx op0 = operands[0];
--- 304,311 ----
  
  (define_expand "load_lockedti"
    [(use (match_operand:TI 0 "quad_int_reg_operand"))
!    (use (match_operand:TI 1 "memory_operand"))
!    (use (match_operand:QI 2 "u1bit_cint_operand"))]
    "TARGET_SYNC_TI"
  {
    rtx op0 = operands[0];
***************
*** 316,322 ****
        operands[1] = op1 = change_address (op1, TImode, new_addr);
      }
  
!   emit_insn (gen_load_lockedpti (pti, op1));
    if (WORDS_BIG_ENDIAN)
      emit_move_insn (op0, gen_lowpart (TImode, pti));
    else
--- 319,325 ----
        operands[1] = op1 = change_address (op1, TImode, new_addr);
      }
  
!   emit_insn (gen_load_lockedpti (pti, op1, operands[2]));
    if (WORDS_BIG_ENDIAN)
      emit_move_insn (op0, gen_lowpart (TImode, pti));
    else
***************
*** 330,340 ****
  (define_insn "load_lockedpti"
    [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
  	(unspec_volatile:PTI
!          [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")] UNSPECV_LL))]
    "TARGET_SYNC_TI
     && !reg_mentioned_p (operands[0], operands[1])
     && quad_int_reg_operand (operands[0], PTImode)"
!   "lqarx %0,%y1"
    [(set_attr "type" "load_l")
     (set_attr "size" "128")])
  
--- 333,344 ----
  (define_insn "load_lockedpti"
    [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
  	(unspec_volatile:PTI
! 	  [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")
! 	   (match_operand:QI 2 "u1bit_cint_operand" "n")] UNSPECV_LL))]
    "TARGET_SYNC_TI
     && !reg_mentioned_p (operands[0], operands[1])
     && quad_int_reg_operand (operands[0], PTImode)"
!   "lqarx %0,%y1,%2"
    [(set_attr "type" "load_l")
     (set_attr "size" "128")])
  
***************
*** 411,417 ****
     (match_operand:SI 7 "const_int_operand")]		;; model fail
    ""
  {
!   rs6000_expand_atomic_compare_and_swap (operands);
    DONE;
  })
  
--- 415,436 ----
     (match_operand:SI 7 "const_int_operand")]		;; model fail
    ""
  {
!   rs6000_expand_atomic_compare_and_swap (operands, false);
!   DONE;
! })
! 
! (define_expand "atomic_compare_and_swap_local<mode>"
!   [(match_operand:SI 0 "int_reg_operand")		;; bool out
!    (match_operand:AINT 1 "int_reg_operand")		;; val out
!    (match_operand:AINT 2 "memory_operand")		;; memory
!    (match_operand:AINT 3 "reg_or_short_operand")	;; expected
!    (match_operand:AINT 4 "int_reg_operand")		;; desired
!    (match_operand:SI 5 "const_int_operand")		;; is_weak
!    (match_operand:SI 6 "const_int_operand")		;; model succ
!    (match_operand:SI 7 "const_int_operand")]		;; model fail
!   ""
! {
!   rs6000_expand_atomic_compare_and_swap (operands, true);
    DONE;
  })
  
diff -Nrcpad gcc-15-20260626/gcc/config/s390/s390.cc gcc-15-20260703/gcc/config/s390/s390.cc
*** gcc-15-20260626/gcc/config/s390/s390.cc	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/s390/s390.cc	Fri Jul  3 22:32:07 2026
*************** s390_rtx_costs (rtx x, machine_mode mode
*** 3944,3956 ****
      case MEM:
        *total = 0;
        return true;
!       case SET: {
  	rtx dst = SET_DEST (x);
  	rtx src = SET_SRC (x);
  
  	switch (GET_CODE (src))
  	  {
! 	    case IF_THEN_ELSE: {
  	      /* Without this a conditional move instruction would be
  		 accounted as 3 * COSTS_N_INSNS (set, if_then_else,
  		 comparison operator).  That's a bit pessimistic.  */
--- 3944,3958 ----
      case MEM:
        *total = 0;
        return true;
!     case SET:
!       {
  	rtx dst = SET_DEST (x);
  	rtx src = SET_SRC (x);
  
  	switch (GET_CODE (src))
  	  {
! 	  case IF_THEN_ELSE:
! 	    {
  	      /* Without this a conditional move instruction would be
  		 accounted as 3 * COSTS_N_INSNS (set, if_then_else,
  		 comparison operator).  That's a bit pessimistic.  */
*************** s390_rtx_costs (rtx x, machine_mode mode
*** 3959,3964 ****
--- 3961,3972 ----
  		return false;
  
  	      rtx cond = XEXP (src, 0);
+ 	      /* Intermediate RTXs may have a non-compare condition as e.g. a
+ 		 constant like r108={(0x1)?r113:r109} which get folded later
+ 		 on.  */
+ 	      if (GET_RTX_CLASS (GET_CODE (cond)) != RTX_COMPARE
+ 		  && GET_RTX_CLASS (GET_CODE (cond)) != RTX_COMM_COMPARE)
+ 		return false;
  	      if (!CC_REG_P (XEXP (cond, 0)) || !CONST_INT_P (XEXP (cond, 1)))
  		return false;
  
*************** s390_rtx_costs (rtx x, machine_mode mode
*** 4017,4023 ****
  	      /* Otherwise just cost the src.  */
  	      *total += rtx_cost (src, mode, SET, 1, speed);
  	    return true;
! 	    case MEM: {
  	      rtx address = XEXP (dst, 0);
  	      rtx tmp;
  	      HOST_WIDE_INT tmp2;
--- 4025,4032 ----
  	      /* Otherwise just cost the src.  */
  	      *total += rtx_cost (src, mode, SET, 1, speed);
  	    return true;
! 	  case MEM:
! 	    {
  	      rtx address = XEXP (dst, 0);
  	      rtx tmp;
  	      HOST_WIDE_INT tmp2;
diff -Nrcpad gcc-15-20260626/gcc/config/s390/s390.md gcc-15-20260703/gcc/config/s390/s390.md
*** gcc-15-20260626/gcc/config/s390/s390.md	Fri Jun 26 22:32:07 2026
--- gcc-15-20260703/gcc/config/s390/s390.md	Fri Jul  3 22:32:07 2026
***************
*** 10023,10028 ****
--- 10023,10029 ----
  	 (pc)))
     (set (match_operand:GPR 4 "nonimmediate_operand" "")
          (plus:GPR (match_dup 1) (match_dup 2)))
+    (clobber (reg:CC CC_REGNUM))
     (clobber (match_scratch:GPR 5 ""))]
    ""
    "#"
diff -Nrcpad gcc-15-20260626/gcc/doc/extend.texi gcc-15-20260703/gcc/doc/extend.texi
*** gcc-15-20260626/gcc/doc/extend.texi	Fri Jun 26 22:32:08 2026
--- gcc-15-20260703/gcc/doc/extend.texi	Fri Jul  3 22:32:07 2026
*************** defined, then the @code{__builtin_set_fp
*** 23198,23203 ****
--- 23198,23226 ----
  fields.  If not defined, the @code{__builtin_set_fpscr_rn} does not return a
  value.  If the @option{-msoft-float} option is used, the
  @code{__builtin_set_fpscr_rn} built-in will not return a value.
+ @defbuiltin{bool __builtin_ppc_atomic_cas_local (@var{type} *@var{ptr}, @var{type} *@var{expected}, @var{type} *@var{desired}, bool @var{weak}, int @var{success_memorder}, int @var{failure_memorder})}
+ This built-in function implements a PowerPC-specific atomic compare and
+ exchange operation.  It behaves identically to the generic
+ @code{__atomic_compare_exchange} built-in function, with one key difference:
+ it uses an EH (Extended Hint) value of 1 in the @code{lbarx}, @code{lharx},
+ @code{lwarx}, or @code{ldarx} instruction (load-and-reserve indexed).
+ 
+ The EH bit provides a hint to the processor that the program will perform a
+ subsequent store to the specified location.  This hint helps optimize lock
+ contention on PowerPC systems by keeping the lock cacheline in the local
+ processor longer, reducing performance penalties from cache coherence protocol
+ traffic.
+ 
+ For details on the behavior and semantics of the arguments, refer to the
+ @code{__atomic_compare_exchange} documentation.
+ 
+ The first three pointer arguments (@var{ptr}, @var{expected}, and
+ @var{desired}) must point to complete types, and the size of the types they
+ point to must be the same and known at compile time.  The types themselves may
+ differ.  The supported type sizes are 1, 2, 4, 8, or 16 bytes.
+ 
+ @enddefbuiltin
+ 
  
  @node Basic PowerPC Built-in Functions Available on ISA 2.05
  @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.05
diff -Nrcpad gcc-15-20260626/gcc/doc/invoke.texi gcc-15-20260703/gcc/doc/invoke.texi
*** gcc-15-20260626/gcc/doc/invoke.texi	Fri Jun 26 22:32:08 2026
--- gcc-15-20260703/gcc/doc/invoke.texi	Fri Jul  3 22:32:07 2026
*************** MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PT
*** 35240,35246 ****
  UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16,
  PREFETCHI, AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16,
  AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512,
! AMX-FP8, AMX-TF32, MOVRS and AMX-MOVRS instruction set support.
  
  @item bonnell
  @itemx atom
--- 35240,35246 ----
  UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16,
  PREFETCHI, AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16,
  AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512,
! AMX-FP8, MOVRS and AMX-MOVRS instruction set support.
  
  @item bonnell
  @itemx atom
diff -Nrcpad gcc-15-20260626/gcc/fortran/match.cc gcc-15-20260703/gcc/fortran/match.cc
*** gcc-15-20260626/gcc/fortran/match.cc	Fri Jun 26 22:32:08 2026
--- gcc-15-20260703/gcc/fortran/match.cc	Fri Jul  3 22:32:08 2026
*************** checks:
*** 3501,3519 ****
  	  goto cleanup;
  	}
  
!       /* Use the machinery for an initialization expression to reduce the
! 	 stop-code to a constant.  */
!       gfc_reduce_init_expr (e);
! 
!       /* Test for F2008 style STOP stop-code.  */
!       if (e->expr_type != EXPR_CONSTANT && f08)
  	{
! 	  gfc_error ("STOP code at %L must be a scalar default CHARACTER or "
! 		     "INTEGER constant expression", &e->where);
! 	  goto cleanup;
  	}
  
!       if (!(e->ts.type == BT_CHARACTER || e->ts.type == BT_INTEGER))
  	{
  	  gfc_error ("STOP code at %L must be either INTEGER or CHARACTER type",
  		     &e->where);
--- 3501,3522 ----
  	  goto cleanup;
  	}
  
!       /* If this is F2008, it could be an init expression.  */
!       if (f08)
  	{
! 	  gfc_reduce_init_expr (e);
! 	  if (e->expr_type != EXPR_CONSTANT)
! 	    {
! 	      gfc_error ("STOP code at %L must be a scalar constant "
! 			 "expression", &e->where);
! 	      goto cleanup;
! 	    }
  	}
  
!       /* For types known at parse time, check immediately.  For BT_UNKNOWN
! 	 (e.g. a forward-referenced contained function) defer to resolve.  */
!       if (e->ts.type != BT_UNKNOWN
! 	  && !(e->ts.type == BT_CHARACTER || e->ts.type == BT_INTEGER))
  	{
  	  gfc_error ("STOP code at %L must be either INTEGER or CHARACTER type",
  		     &e->where);
diff -Nrcpad gcc-15-20260626/gcc/fortran/resolve.cc gcc-15-20260703/gcc/fortran/resolve.cc
*** gcc-15-20260626/gcc/fortran/resolve.cc	Fri Jun 26 22:32:08 2026
--- gcc-15-20260703/gcc/fortran/resolve.cc	Fri Jul  3 22:32:08 2026
*************** start:
*** 13465,13470 ****
--- 13465,13489 ----
  
  	case EXEC_STOP:
  	case EXEC_ERROR_STOP:
+ 	  if (code->expr1 != NULL && t)
+ 	    {
+ 	      if (!(code->expr1->ts.type == BT_CHARACTER
+ 		    || code->expr1->ts.type == BT_INTEGER))
+ 		gfc_error ("STOP code at %L must be either INTEGER or CHARACTER "
+ 			   "type", &code->expr1->where);
+ 	      else if (code->expr1->rank != 0)
+ 		gfc_error ("STOP code at %L must be scalar",
+ 			   &code->expr1->where);
+ 	      else if (code->expr1->ts.type == BT_CHARACTER
+ 		       && code->expr1->ts.kind != gfc_default_character_kind)
+ 		gfc_error ("STOP code at %L must be default character KIND=%d",
+ 			   &code->expr1->where, (int) gfc_default_character_kind);
+ 	      else if (code->expr1->ts.type == BT_INTEGER
+ 		       && code->expr1->ts.kind != gfc_default_integer_kind)
+ 		gfc_notify_std (GFC_STD_F2018, "STOP code at %L must be default "
+ 				"integer KIND=%d", &code->expr1->where,
+ 				(int) gfc_default_integer_kind);
+ 	    }
  	  if (code->expr2 != NULL
  	      && (code->expr2->ts.type != BT_LOGICAL
  		  || code->expr2->rank != 0))
diff -Nrcpad gcc-15-20260626/gcc/ira.cc gcc-15-20260703/gcc/ira.cc
*** gcc-15-20260626/gcc/ira.cc	Fri Jun 26 22:32:08 2026
--- gcc-15-20260703/gcc/ira.cc	Fri Jul  3 22:32:08 2026
*************** combine_and_move_insns (void)
*** 3894,3899 ****
--- 3894,3900 ----
  	continue;
  
        rtx_insn *use_insn = 0;
+       bool multiple_insns = false;
        for (df_ref use = DF_REG_USE_CHAIN (regno);
  	   use;
  	   use = DF_REF_NEXT_REG (use))
*************** combine_and_move_insns (void)
*** 3901,3911 ****
  	  {
  	    if (DEBUG_INSN_P (DF_REF_INSN (use)))
  	      continue;
! 	    gcc_assert (!use_insn);
  	    use_insn = DF_REF_INSN (use);
  	  }
        gcc_assert (use_insn);
  
        /* Don't substitute into jumps.  indirect_jump_optimize does
  	 this for anything we are prepared to handle.  */
        if (JUMP_P (use_insn))
--- 3902,3921 ----
  	  {
  	    if (DEBUG_INSN_P (DF_REF_INSN (use)))
  	      continue;
! 	    if (use_insn && DF_REF_INSN (use) != use_insn)
! 	      {
! 		multiple_insns = true;
! 		break;
! 	      }
  	    use_insn = DF_REF_INSN (use);
  	  }
        gcc_assert (use_insn);
  
+       /* If a register is used by more than one insn, we cannot trivially move
+ 	 or delete the definition anymore.  */
+       if (multiple_insns)
+ 	continue;
+ 
        /* Don't substitute into jumps.  indirect_jump_optimize does
  	 this for anything we are prepared to handle.  */
        if (JUMP_P (use_insn))
diff -Nrcpad gcc-15-20260626/gcc/testsuite/ChangeLog gcc-15-20260703/gcc/testsuite/ChangeLog
*** gcc-15-20260626/gcc/testsuite/ChangeLog	Fri Jun 26 22:32:11 2026
--- gcc-15-20260703/gcc/testsuite/ChangeLog	Fri Jul  3 22:32:10 2026
***************
*** 1,3 ****
--- 1,82 ----
+ 2026-07-02  Christophe Lyon  <christophe.lyon@arm.com>
+ 
+ 	Backported from master:
+ 	2026-01-27  Christophe Lyon  <christophe.lyon@arm.com>
+ 
+ 	* gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Update expected
+ 	code.
+ 
+ 2026-07-01  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-26  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR target/125972
+ 	* gcc.target/s390/pr125972.c: New test.
+ 
+ 2026-07-01  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/opt109.adb: New test.
+ 	* gnat.dg/opt109_pkg.ads, gnat.dg/opt109_pkg.adb: New helper.
+ 
+ 2026-07-01  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-06-30  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 		    Surya Kumari Jangala  <jskumari@linux.ibm.com>
+ 
+ 	* gcc.target/powerpc/acmp-tst-32bit.c: New test.
+ 	* gcc.target/powerpc/acmp-tst.c: New test.
+ 	* gcc.target/powerpc/acmp-tst-indexed.c: New test.
+ 
+ 2026-06-30  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-12  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR rtl-optimization/125173
+ 	* gcc.dg/pr125173-1.c: New test.
+ 
+ 2026-06-30  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2026-04-22  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/124908
+ 	* gcc.target/aarch64/sve/acle/general/ld1rq_2.c: New test.
+ 
+ 2026-06-29  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	Backported from master:
+ 	2026-06-23  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	PR target/125818
+ 	* gcc.target/aarch64/torture/pr125818.c: New test.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-28  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125469
+ 	* gcc.target/i386/apx-nf-pr125469.c: New test.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125992
+ 	* gcc.target/s390/pr125992.c: New test.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-06  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125611
+ 	* gcc.target/i386/ssse3-pr125611.c: New test.
+ 
  2026-06-25  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.dg/pr125173-1.c gcc-15-20260703/gcc/testsuite/gcc.dg/pr125173-1.c
*** gcc-15-20260626/gcc/testsuite/gcc.dg/pr125173-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.dg/pr125173-1.c	Fri Jul  3 22:32:12 2026
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O1 -fno-forward-propagate --param=max-cse-insns=0" } */
+ 
+ int a;
+ volatile short b;
+ 
+ struct
+ {
+   char c;
+   int d;
+ } s;
+ 
+ void
+ foo ()
+ {
+   __asm__ ("":"+m" (b), "+m" (s.d), "+m" (a));
+ }
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_2.c gcc-15-20260703/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_2.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_2.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_2.c	Fri Jul  3 22:32:13 2026
***************
*** 0 ****
--- 1,37 ----
+ /* PR target/124908 */
+ /* { dg-options "-O2 -msve-vector-bits=128" } */
+ 
+ #include <arm_sve.h>
+ 
+ /* Verify that folding svld1rq does not ICE with -msve-vector-bits=128.  */
+ 
+ svuint8_t
+ f_u8 (const uint8_t *p)
+ {
+   return svld1rq_u8 (svptrue_b8 (), p);
+ }
+ 
+ svint8_t
+ f_s8 (const int8_t *p)
+ {
+   return svld1rq_s8 (svptrue_b8 (), p);
+ }
+ 
+ svuint16_t
+ f_u16 (const uint16_t *p)
+ {
+   return svld1rq_u16 (svptrue_b16 (), p);
+ }
+ 
+ svuint32_t
+ f_u32 (const uint32_t *p)
+ {
+   return svld1rq_u32 (svptrue_b32 (), p);
+ }
+ 
+ svfloat64_t
+ f_f64 (const float64_t *p)
+ {
+   return svld1rq_f64 (svptrue_b64 (), p);
+ }
+ 
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/aarch64/torture/pr125818.c gcc-15-20260703/gcc/testsuite/gcc.target/aarch64/torture/pr125818.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/aarch64/torture/pr125818.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.target/aarch64/torture/pr125818.c	Fri Jul  3 22:32:13 2026
***************
*** 0 ****
--- 1,6 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options "-march=armv8.2-a+sve" } */
+ #include <arm_sve.h>
+ void f(svfloat32x2_t *tp, const svfloat32x2_t *tuple, const svfloat32_t *vp) {
+   *tp = svset2_f32(*tuple, 0, *vp);
+ }
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/ifcvt-size-check.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/ifcvt-size-check.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/ifcvt-size-check.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/ifcvt-size-check.c	Fri Jul  3 22:32:13 2026
***************
*** 1,6 ****
  /* { dg-do assemble } */
! /* { dg-options "-mthumb -Os " }  */
! /* { dg-require-effective-target arm_thumb1_ok } */
  
  int
  test (unsigned char iov_len, int count, int i)
--- 1,7 ----
  /* { dg-do assemble } */
! /* { dg-require-effective-target arm_arch_v4t_thumb_ok } */
! /* { dg-options "-Os" } */
! /* { dg-add-options arm_arch_v4t_thumb } */
  
  int
  test (unsigned char iov_len, int count, int i)
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts-2.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts-2.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts-2.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts-2.c	Fri Jul  3 22:32:13 2026
***************
*** 1,5 ****
! /* { dg-do assemble } */
! /* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */
  
  extern void foo2 (short*);
  
--- 1,4 ----
! /* { dg-options "-Os -fdump-tree-ivopts" } */
  
  extern void foo2 (short*);
  
*************** tr4 (short array[], int n)
*** 14,17 ****
  
  /* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */
  /* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */
- /* { dg-final { object-size text <= 26 { target { arm_thumb2 && { ! arm*-*-uclinuxfdpiceabi } } } } } */
--- 13,15 ----
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts-3.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts-3.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts-3.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts-3.c	Fri Jul  3 22:32:13 2026
***************
*** 1,5 ****
! /* { dg-do assemble } */
! /* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */
  
  extern unsigned int foo2 (short*) __attribute__((pure));
  
--- 1,4 ----
! /* { dg-options "-Os -fdump-tree-ivopts" } */
  
  extern unsigned int foo2 (short*) __attribute__((pure));
  
*************** tr3 (short array[], unsigned int n)
*** 16,19 ****
  /* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */
  /* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */
  /* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */
- /* { dg-final { object-size text <= 30 { target { arm_thumb2 && { ! arm*-*-uclinuxfdpiceabi } } } } } */
--- 15,17 ----
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts-4.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts-4.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts-4.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts-4.c	Fri Jul  3 22:32:13 2026
***************
*** 1,5 ****
! /* { dg-do assemble } */
! /* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */
  
  extern unsigned int foo (int*) __attribute__((pure));
  
--- 1,4 ----
! /* { dg-options "-Os -fdump-tree-ivopts" } */
  
  extern unsigned int foo (int*) __attribute__((pure));
  
*************** tr2 (int array[], int n)
*** 17,20 ****
  /* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */
  /* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */
  /* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */
- /* { dg-final { object-size text <= 36 { target { arm_thumb2 && { ! arm*-*-uclinuxfdpiceabi } } } } } */
--- 16,18 ----
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts-5.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts-5.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts-5.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts-5.c	Fri Jul  3 22:32:13 2026
***************
*** 1,5 ****
! /* { dg-do assemble } */
! /* { dg-options "-Os -fdump-tree-ivopts -save-temps" } */
  
  extern unsigned int foo (int*) __attribute__((pure));
  
--- 1,4 ----
! /* { dg-options "-Os -fdump-tree-ivopts" } */
  
  extern unsigned int foo (int*) __attribute__((pure));
  
*************** tr1 (int array[], unsigned int n)
*** 16,19 ****
  /* { dg-final { scan-tree-dump-times "PHI <ivtmp" 1 "ivopts"} } */
  /* { dg-final { scan-tree-dump-times "PHI <x" 0 "ivopts"} } */
  /* { dg-final { scan-tree-dump-times ", x" 0 "ivopts"} } */
- /* { dg-final { object-size text <= 30 { target { arm_thumb2 && { ! arm*-*-uclinuxfdpiceabi } } } } } */
--- 15,17 ----
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/ivopts.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/ivopts.c	Fri Jul  3 22:32:13 2026
***************
*** 1,5 ****
! /* { dg-do assemble } */
! /* { dg-options "-Os -fdump-tree-ivopts -save-temps -fno-tree-loop-distribute-patterns" } */
  
  void
  tr5 (short array[], int n)
--- 1,4 ----
! /* { dg-options "-Os -fdump-tree-ivopts -fno-tree-loop-distribute-patterns" } */
  
  void
  tr5 (short array[], int n)
*************** tr5 (short array[], int n)
*** 11,16 ****
  }
  
  /* { dg-final { scan-tree-dump-times "PHI <" 1 "ivopts"} } */
- /* { dg-final { object-size text <= 20 { target { arm_thumb2_no_arm_v8_1m_lob } } } } */
- /* { dg-final { object-size text <= 32 { target { arm_nothumb && { ! arm_iwmmxt_ok } } } } } */
  /* { dg-final { object-size text <= 36 { target { arm_nothumb && arm_iwmmxt_ok }  } } } */
--- 10,13 ----
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/max-insns-skipped.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/max-insns-skipped.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/max-insns-skipped.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/max-insns-skipped.c	Fri Jul  3 22:32:13 2026
***************
*** 1,5 ****
! /* { dg-do assemble { target arm_thumb2 } } */
! /* { dg-options " -Os " } */
  
  int t (int a, int b, int c, int d)
  {
--- 1,6 ----
! /* { dg-require-effective-target arm_arch_v7a_thumb_ok } */
! /* { dg-options "-Os" } */
! /* { dg-add-options arm_arch_v7a_thumb } */
  
  int t (int a, int b, int c, int d)
  {
*************** int t (int a, int b, int c, int d)
*** 18,21 ****
    return r;
  }
  
! /* { dg-final { object-size text <= 40 } } */
--- 19,22 ----
    return r;
  }
  
! /* { dg-final { scan-assembler-not {\tit[tf]*\t} } } */
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c	Fri Jul  3 22:32:13 2026
*************** foo (float32_t a)
*** 24,30 ****
--- 24,35 ----
  /*
  **foo1:
  **	...
+ ** (
  **	ldr	r[0-9]+, .L.*
+ ** |
+ **	movw	(r[0-9]+), #52429
+ **	movt	\1, 16268
+ ** )
  **	vdup.32	q[0-9]+, r[0-9]+
  **	...
  */
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/pr43597.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/pr43597.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/pr43597.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/pr43597.c	Fri Jul  3 22:32:13 2026
***************
*** 1,6 ****
! /* { dg-do assemble } */
! /* { dg-options "-Os -save-temps -mthumb" } */
! /* { dg-require-effective-target arm_thumb2_ok } */
  
  extern int bar ();
  extern void bar2 (int);
--- 1,6 ----
! /* { dg-require-effective-target arm_arch_v7a_thumb_ok } */
! /* { dg-options "-Os" } */
! /* { dg-add-options arm_arch_v7a_thumb } */
  
  extern int bar ();
  extern void bar2 (int);
*************** foo4 ()
*** 24,27 ****
  
  /* { dg-final { scan-assembler-times "sub" 1 } } */
  /* { dg-final { scan-assembler-times "cmp" 0 } } */
- /* { dg-final { object-size text <= 30 { target { ! arm*-*-uclinuxfdpiceabi } } } } */
--- 24,26 ----
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/pr63210.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/pr63210.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/pr63210.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/pr63210.c	Fri Jul  3 22:32:13 2026
***************
*** 1,8 ****
  /* { dg-do assemble } */
! /* { dg-options "-mthumb -Os " }  */
! /* { dg-require-effective-target arm_thumb1_ok } */
! /* { dg-skip-if "do not test on armv4t" { *-*-* } { "-march=armv4t" } } */
! /* { dg-additional-options "-march=armv5t" {target arm_arch_v5t_ok} } */
  
  int foo1 (int c);
  int foo2 (int c);
--- 1,7 ----
  /* { dg-do assemble } */
! /* { dg-options "-Os" }  */
! /* { dg-require-effective-target arm_arch_v5t_thumb_ok } */
! /* { dg-add-options arm_arch_v5t_thumb } */
  
  int foo1 (int c);
  int foo2 (int c);
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c gcc-15-20260703/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c	Fri Jun 26 22:32:14 2026
--- gcc-15-20260703/gcc/testsuite/gcc.target/arm/split-live-ranges-for-shrink-wrap.c	Fri Jul  3 22:32:13 2026
***************
*** 1,8 ****
! /* { dg-do assemble } */
! /* { dg-options "-mthumb -Os -fdump-rtl-ira " }  */
! /* { dg-require-effective-target arm_thumb1_ok } */
! /* { dg-skip-if "do not test on armv4t" { *-*-* } { "-march=armv4t" } } */
! /* { dg-additional-options "-march=armv5t" {target arm_arch_v5t_ok} } */
  
  int foo (char *, char *, int);
  int test (int d, char * out, char *in, int len)
--- 1,6 ----
! /* { dg-options "-Os -fdump-rtl-ira " } */
! /* { dg-require-effective-target arm_arch_v5t_thumb_ok } */
! /* { dg-add-options arm_arch_v5t_thumb } */
  
  int foo (char *, char *, int);
  int test (int d, char * out, char *in, int len)
*************** int test (int d, char * out, char *in, i
*** 11,15 ****
      foo (out, in, len);
    return 0;
  }
- /* { dg-final { object-size text <= 20 } } */
  /* { dg-final { scan-rtl-dump-not "Split live-range of register" "ira" } } */
--- 9,12 ----
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/i386/apx-nf-pr125469.c gcc-15-20260703/gcc/testsuite/gcc.target/i386/apx-nf-pr125469.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/i386/apx-nf-pr125469.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.target/i386/apx-nf-pr125469.c	Fri Jul  3 22:32:13 2026
***************
*** 0 ****
--- 1,11 ----
+ /* PR target/125469 */
+ /* { dg-do compile { target int128 } } */
+ /* { dg-options "-Ofast -mapx-features=nf" } */
+ 
+ int s;
+ 
+ void
+ foo ()
+ {
+   s /= ((__int128) 0x33333333333333333333333333333333uwb) + 1i;
+ }
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/i386/ssse3-pr125611.c gcc-15-20260703/gcc/testsuite/gcc.target/i386/ssse3-pr125611.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/i386/ssse3-pr125611.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.target/i386/ssse3-pr125611.c	Fri Jul  3 22:32:14 2026
***************
*** 0 ****
--- 1,12 ----
+ /* PR target/125611 */
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -mssse3 -mno-sse4.1" } */
+ 
+ typedef __attribute__((__vector_size__(16))) short V;
+ struct __attribute__((__packed__)) { V v[4]; } *u;
+ 
+ void
+ foo (void)
+ {
+   u->v[2] &= __builtin_ia32_pmulhrsw128 (u->v[0], u->v[1]);
+ }
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/powerpc/acmp-tst-32bit.c gcc-15-20260703/gcc/testsuite/gcc.target/powerpc/acmp-tst-32bit.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/powerpc/acmp-tst-32bit.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.target/powerpc/acmp-tst-32bit.c	Fri Jul  3 22:32:14 2026
***************
*** 0 ****
--- 1,61 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target ilp32 } */
+ 
+ /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+ 
+ bool
+ word_exchange_qi (signed char *ptr, signed char *expected, signed char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uqi (unsigned char *ptr, unsigned char *expected,
+                    unsigned char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_hi (short *ptr, short *expected, short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_shi (signed short *ptr, signed short *expected,
+                    signed short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uhi (unsigned short *ptr, unsigned short *expected,
+                    unsigned short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_si (int *ptr, int *expected, int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_ssi (signed int *ptr, signed int *expected, signed int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_usi (unsigned int *ptr, unsigned int *expected,
+                    unsigned int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ 
+ /* { dg-final { scan-assembler-times {\mlbarx +[0-9]+,[0-9]+,[0-9]+,1} 2 } } */
+ /* { dg-final { scan-assembler-times {\mlharx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */
+ /* { dg-final { scan-assembler-times {\mlwarx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/powerpc/acmp-tst-indexed.c gcc-15-20260703/gcc/testsuite/gcc.target/powerpc/acmp-tst-indexed.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/powerpc/acmp-tst-indexed.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.target/powerpc/acmp-tst-indexed.c	Fri Jul  3 22:32:14 2026
***************
*** 0 ****
--- 1,165 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+ 
+ // Need power8 for l<b,h,q>arx
+ /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+ 
+ typedef struct udt_1
+ {
+   char *a;
+ } udt_1t;
+ typedef struct udt_2
+ {
+   char a;
+   char b;
+ } udt_2t;
+ typedef struct udt_4
+ {
+   short a;
+   short b;
+ } udt_4t;
+ typedef struct udt_8
+ {
+   int a;
+   int b;
+ } udt_8t;
+ bool
+ word_exchange_nqi (char *ptr, char *expected, char *desired,
+ 		   unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_qi (signed char *ptr, signed char *expected, signed char *desired,
+ 		  unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uqi (unsigned char *ptr, unsigned char *expected,
+                    unsigned char *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_hi (short *ptr, short *expected, short *desired,
+ 		  unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_shi (signed short *ptr, signed short *expected,
+                    signed short *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uhi (unsigned short *ptr, unsigned short *expected,
+                    unsigned short *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_si (int *ptr, int *expected, int *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_ssi (signed int *ptr, signed int *expected, signed int *desired,
+ 		   unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_usi (unsigned int *ptr, unsigned int *expected,
+                    unsigned int *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_di (long long *ptr, long long *expected, long long *desired,
+ 		  unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_sdi (signed long long *ptr, signed long long *expected,
+                    signed long long *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udi (unsigned long long *ptr, unsigned long long *expected,
+                    unsigned long long *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f32 (float *ptr, float *expected, float *desired,
+ 		   unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f64 (double *ptr, double *expected, double *desired,
+ 		   unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_1 (udt_1t *ptr, udt_1t *expected, udt_1t *desired,
+ 		     unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_2 (udt_2t *ptr, udt_2t *expected, udt_2t *desired,
+ 		     unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_4 (udt_4t *ptr, udt_4t *expected, udt_4t *desired,
+ 		     unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_8 (udt_8t *ptr, udt_8t *expected, udt_8t *desired,
+ 		     unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ 
+ /* Test if indexed mode addresses are used, r6 must be used which corresponds
+    to the argument n in all functions.  */
+ 
+ /* { dg-final { scan-assembler-times {\mlbarx +[0-9]+,[0-9]+,6,1} 3 } } */
+ /* { dg-final { scan-assembler-times {\mstbcx. +[0-9]+,[0-9]+,6} 3 } } */
+ 
+ /* { dg-final { scan-assembler-times {\mlharx +[0-9]+,[0-9]+,6,1} 4 } } */
+ /* { dg-final { scan-assembler-times {\msthcx. +[0-9]+,[0-9]+,6} 4 } } */
+ 
+ /* { dg-final { scan-assembler-times {\mlwarx +[0-9]+,[0-9]+,6,1} 5 } } */
+ /* { dg-final { scan-assembler-times {\mstwcx. +[0-9]+,[0-9]+,6} 5 } } */
+ 
+ /* { dg-final { scan-assembler-times {\mldarx +[0-9]+,[0-9]+,6,1} 6 } } */
+ /* { dg-final { scan-assembler-times {\mstdcx. +[0-9]+,[0-9]+,6} 6 } } */
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/powerpc/acmp-tst.c gcc-15-20260703/gcc/testsuite/gcc.target/powerpc/acmp-tst.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/powerpc/acmp-tst.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.target/powerpc/acmp-tst.c	Fri Jul  3 22:32:14 2026
***************
*** 0 ****
--- 1,176 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+ 
+ // Need power8 for l<b,h,q>arx
+ /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+ 
+ typedef struct udt_1
+ {
+   char *a;
+ } udt_1t;
+ typedef struct udt_2
+ {
+   char a;
+   char b;
+ } udt_2t;
+ typedef struct udt_4
+ {
+   short a;
+   short b;
+ } udt_4t;
+ typedef struct udt_8
+ {
+   int a;
+   int b;
+ } udt_8t;
+ typedef struct udt_16
+ {
+   long long a;
+   long long b;
+ } udt_16t;
+ bool
+ word_exchange_nqi (char *ptr, char *expected, char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_qi (signed char *ptr, signed char *expected, signed char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uqi (unsigned char *ptr, unsigned char *expected,
+                    unsigned char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_hi (short *ptr, short *expected, short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_shi (signed short *ptr, signed short *expected,
+                    signed short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uhi (unsigned short *ptr, unsigned short *expected,
+                    unsigned short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_si (int *ptr, int *expected, int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_ssi (signed int *ptr, signed int *expected, signed int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_usi (unsigned int *ptr, unsigned int *expected,
+                    unsigned int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_di (long long *ptr, long long *expected, long long *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_sdi (signed long long *ptr, signed long long *expected,
+                    signed long long *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udi (unsigned long long *ptr, unsigned long long *expected,
+                    unsigned long long *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_sti (signed __int128 *ptr, signed __int128 *expected,
+                    signed __int128 *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uti (unsigned __int128 *ptr, unsigned __int128 *expected,
+                    unsigned __int128 *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f32 (float *ptr, float *expected, float *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f64 (double *ptr, double *expected, double *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f128 (__ieee128 *ptr, __ieee128 *expected, __ieee128 *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_1 (udt_1t *ptr, udt_1t *expected, udt_1t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_2 (udt_2t *ptr, udt_2t *expected, udt_2t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_4 (udt_4t *ptr, udt_4t *expected, udt_4t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_8 (udt_8t *ptr, udt_8t *expected, udt_8t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_16 (udt_16t *ptr, udt_16t *expected, udt_16t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ 
+ /* { dg-final { scan-assembler-times {\mlbarx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */
+ /* { dg-final { scan-assembler-times {\mlharx +[0-9]+,[0-9]+,[0-9]+,1} 4 } } */
+ /* { dg-final { scan-assembler-times {\mlwarx +[0-9]+,[0-9]+,[0-9]+,1} 5 } } */
+ /* { dg-final { scan-assembler-times {\mldarx +[0-9]+,[0-9]+,[0-9]+,1} 6 } } */
+ /* { dg-final { scan-assembler-times {\mlqarx +[0-9]+,[0-9]+,[0-9]+,1} 4 } } */
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/s390/pr125972.c gcc-15-20260703/gcc/testsuite/gcc.target/s390/pr125972.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/s390/pr125972.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.target/s390/pr125972.c	Fri Jul  3 22:32:14 2026
***************
*** 0 ****
--- 1,20 ----
+ /* { dg-do compile { target int128 } } */
+ /* { dg-options "-march=z16 -O3" } */
+ 
+ int a, b, c;
+ long d, e;
+ int *f;
+ __int128 g;
+ void h() {
+   g = 0;
+   for (; g <= 33; ++g) {
+     int *i = &c;
+     *i = d - a;
+     if (*i) {
+       c = 0;
+       for (; c <= 8; ++c)
+         f = &b;
+     } else
+       ++e;
+   }
+ }
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gcc.target/s390/pr125992.c gcc-15-20260703/gcc/testsuite/gcc.target/s390/pr125992.c
*** gcc-15-20260626/gcc/testsuite/gcc.target/s390/pr125992.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gcc.target/s390/pr125992.c	Fri Jul  3 22:32:14 2026
***************
*** 0 ****
--- 1,41 ----
+ /* PR target/125992 */
+ /* { dg-do run { target s390_useable_hw } } */
+ /* { dg-options "-O2 -march=z13" } */
+ 
+ long a, b, c, d[4];
+ 
+ [[gnu::noipa]] long
+ foo ()
+ {
+   return d[c++];
+ }
+ 
+ [[gnu::noipa]] void
+ bar ()
+ {
+   long e = 0;
+   for (;;)
+     {
+       e += a;
+       a = foo ();
+       if (b + a > e)
+ 	return;
+       if (a == 0)
+ 	break;
+       if (a > 0)
+ 	b += a;
+     }
+ }
+ 
+ int
+ main ()
+ {
+   a = 16;
+   b = -64;
+   c = 0;
+   d[0] = 64;
+   d[1] = 128;
+   bar ();
+   if (b != 0)
+     __builtin_abort ();
+ }
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gfortran.dg/stop_function_code_1.f90 gcc-15-20260703/gcc/testsuite/gfortran.dg/stop_function_code_1.f90
*** gcc-15-20260626/gcc/testsuite/gfortran.dg/stop_function_code_1.f90	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gfortran.dg/stop_function_code_1.f90	Fri Jul  3 22:32:15 2026
***************
*** 0 ****
--- 1,14 ----
+ ! { dg-do compile }
+ ! PR fortran/126018 - Stop code may be a function call (CHARACTER or INTEGER)
+ program p
+   implicit none
+   error stop character_stop ()   ! was: "must be either INTEGER or CHARACTER"
+   stop integer_stop ()           ! likewise for integer
+ contains
+   character (1) function character_stop ()
+     character_stop = "a"
+   end function character_stop
+   integer function integer_stop ()
+     integer_stop = 1
+   end function integer_stop
+ end program p
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gnat.dg/opt109.adb gcc-15-20260703/gcc/testsuite/gnat.dg/opt109.adb
*** gcc-15-20260626/gcc/testsuite/gnat.dg/opt109.adb	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gnat.dg/opt109.adb	Fri Jul  3 22:32:15 2026
***************
*** 0 ****
--- 1,13 ----
+ -- { dg-do run }
+ -- { dg-options "-O" }
+ 
+ with Opt109_Pkg; use Opt109_Pkg;
+ 
+ procedure Opt109 is
+   S : constant String := "Hello World!";
+   R : constant Rec := F (S);
+ begin
+   if R.B.Data.all /= S then
+     raise Program_Error;
+   end if;
+ end;
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gnat.dg/opt109_pkg.adb gcc-15-20260703/gcc/testsuite/gnat.dg/opt109_pkg.adb
*** gcc-15-20260626/gcc/testsuite/gnat.dg/opt109_pkg.adb	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gnat.dg/opt109_pkg.adb	Fri Jul  3 22:32:15 2026
***************
*** 0 ****
--- 1,16 ----
+ package body Opt109_Pkg is
+ 
+    function F (Value : String) return Rec is
+    begin
+       if Value'Length > Max then
+          return Result : Rec (Is_Small => False) do
+             Result.B.Data := new String'(Value);
+          end return;
+       else
+          return Result : Rec (Is_Small => True) do
+             Result.S.Data (Value'Length + 1 .. Max) := (others => ' ');
+          end return;
+       end if;
+    end;
+ 
+ end Opt109_Pkg;
diff -Nrcpad gcc-15-20260626/gcc/testsuite/gnat.dg/opt109_pkg.ads gcc-15-20260703/gcc/testsuite/gnat.dg/opt109_pkg.ads
*** gcc-15-20260626/gcc/testsuite/gnat.dg/opt109_pkg.ads	Thu Jan  1 00:00:00 1970
--- gcc-15-20260703/gcc/testsuite/gnat.dg/opt109_pkg.ads	Fri Jul  3 22:32:15 2026
***************
*** 0 ****
--- 1,33 ----
+ with System;
+ 
+ package Opt109_Pkg is
+ 
+    Max : constant Natural := 7;
+    subtype Small_String_Size is Natural range 0 .. Max;
+ 
+    type Small_String is record
+       Is_Small : Boolean;
+       Length   : Small_String_Size;
+       Data     : aliased String (1 .. Max);
+    end record;
+ 
+    type Big_String_Access is access all String;
+ 
+    type Big_String is record
+       Data : Big_String_Access := null;
+    end record;
+ 
+    for Big_String use record
+       Data at 0 range 0 .. System.Word_Size - 1;
+    end record;
+ 
+    type Rec (Is_Small : Boolean := True) is record
+       case Is_Small is
+          when True  => S : Small_String;
+          when False => B : Big_String;
+       end case;
+    end record with Unchecked_Union;
+ 
+    function F (Value : String) return Rec;
+ 
+ end Opt109_Pkg;
diff -Nrcpad gcc-15-20260626/gcc/testsuite/lib/target-supports.exp gcc-15-20260703/gcc/testsuite/lib/target-supports.exp
*** gcc-15-20260626/gcc/testsuite/lib/target-supports.exp	Fri Jun 26 22:32:16 2026
--- gcc-15-20260703/gcc/testsuite/lib/target-supports.exp	Fri Jul  3 22:32:16 2026
*************** foreach { armfunc armflag armdefs } {
*** 6055,6060 ****
--- 6055,6061 ----
  	v6m "-march=armv6-m -mthumb -mfloat-abi=soft" __ARM_ARCH_6M__
  	v7a "-march=armv7-a+fp" __ARM_ARCH_7A__
  	v7a_arm "-march=armv7-a+fp -marm" "__ARM_ARCH_7A__ && !__thumb__"
+ 	v7a_thumb "-march=armv7-a+fp -mthumb" "__ARM_ARCH_7A__ && __thumb__"
  	v7a_fp_hard "-march=armv7-a+fp -mfpu=auto -mfloat-abi=hard" __ARM_ARCH_7A__
  	v7a_neon "-march=armv7-a+simd -mfpu=auto -mfloat-abi=softfp" "__ARM_ARCH_7A__ && __ARM_NEON__"
  	v7a_neon_thumb "-march=armv7-a+simd -mfpu=auto -mfloat-abi=softfp -mthumb" "__ARM_ARCH_7A__ && __ARM_NEON__ && __thumb__"
diff -Nrcpad gcc-15-20260626/gcc/tree-ssa-structalias.cc gcc-15-20260703/gcc/tree-ssa-structalias.cc
*** gcc-15-20260626/gcc/tree-ssa-structalias.cc	Fri Jun 26 22:32:17 2026
--- gcc-15-20260703/gcc/tree-ssa-structalias.cc	Fri Jul  3 22:32:16 2026
*************** static void
*** 6782,6793 ****
  set_uids_in_ptset (bitmap into, bitmap from, struct pt_solution *pt,
  		   tree fndecl)
  {
    unsigned int i;
    bitmap_iterator bi;
-   varinfo_t escaped_vi = get_varinfo (find (escaped_id));
-   varinfo_t escaped_return_vi = get_varinfo (find (escaped_return_id));
-   bool everything_escaped
-     = escaped_vi->solution && bitmap_bit_p (escaped_vi->solution, anything_id);
  
    EXECUTE_IF_SET_IN_BITMAP (from, 0, i, bi)
      {
--- 6782,6796 ----
  set_uids_in_ptset (bitmap into, bitmap from, struct pt_solution *pt,
  		   tree fndecl)
  {
+   const varinfo_t escaped_vi = get_varinfo (find (escaped_id));
+   const varinfo_t escaped_return_vi = get_varinfo (find (escaped_return_id));
+   const bool everything_escaped
+     = escaped_vi->solution && bitmap_bit_p (escaped_vi->solution, anything_id);
+   const bool everything_escaped_return
+     = escaped_return_vi->solution
+       && bitmap_bit_p (escaped_return_vi->solution, anything_id);
    unsigned int i;
    bitmap_iterator bi;
  
    EXECUTE_IF_SET_IN_BITMAP (from, 0, i, bi)
      {
*************** set_uids_in_ptset (bitmap into, bitmap f
*** 6803,6810 ****
  	  pt->vars_contains_escaped = true;
  	  pt->vars_contains_escaped_heap |= vi->is_heap_var;
  	}
!       if (escaped_return_vi->solution
! 	  && bitmap_bit_p (escaped_return_vi->solution, i))
  	pt->vars_contains_escaped_heap |= vi->is_heap_var;
  
        if (vi->is_restrict_var)
--- 6806,6815 ----
  	  pt->vars_contains_escaped = true;
  	  pt->vars_contains_escaped_heap |= vi->is_heap_var;
  	}
! 
!       if (everything_escaped_return
! 	  || (escaped_return_vi->solution
! 	      && bitmap_bit_p (escaped_return_vi->solution, i)))
  	pt->vars_contains_escaped_heap |= vi->is_heap_var;
  
        if (vi->is_restrict_var)
diff -Nrcpad gcc-15-20260626/libgcc/config/avr/libf7/ChangeLog gcc-15-20260703/libgcc/config/avr/libf7/ChangeLog
*** gcc-15-20260626/libgcc/config/avr/libf7/ChangeLog	Fri Jun 26 22:32:17 2026
--- gcc-15-20260703/libgcc/config/avr/libf7/ChangeLog	Fri Jul  3 22:32:16 2026
***************
*** 1,3 ****
--- 1,21 ----
+ 2026-06-28  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-06-28  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/125752
+ 	* libf7.c (d_to_ufx, d_to_sfx): Remove prototypes.
+ 	(__fractdfda, __fractdfuda, __fractdfta, __fractdfuta)
+ 	(__fractdfdq, __fractdfudq): Move implementation to...
+ 	* libf7-asm.sx: ...here.
+ 	(d_to_fx64): Remove.
+ 	* libf7-common.mk (F7_ASM_PARTS): Add D2dq, D2udq, D2da,
+ 	D2uda, D2ta, D2uta.
+ 	(F7F_asm): Remove d_to_fx64.
+ 	* t-libf7 (LIBF7_DF_CONV): Remove fractdfda, fractdfta,
+ 	fractdfdq, fractdfuda, fractdfuta, fractdfudq.
+ 	* f7-renames.h: Rebuild.
+ 
  2026-06-12  Georg-Johann Lay  <avr@gjlay.de>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260626/libgcc/config/avr/libf7/f7-renames.h gcc-15-20260703/libgcc/config/avr/libf7/f7-renames.h
*** gcc-15-20260626/libgcc/config/avr/libf7/f7-renames.h	Fri Jun 26 22:32:17 2026
--- gcc-15-20260703/libgcc/config/avr/libf7/f7-renames.h	Fri Jul  3 22:32:16 2026
***************
*** 222,228 ****
  #define f7_sqrt16_floor_asm __f7_sqrt16_floor_asm
  #define f7_lshrdi3_asm __f7_lshrdi3_asm
  #define f7_ashldi3_asm __f7_ashldi3_asm
- #define f7_d_to_fx64_asm __f7_d_to_fx64_asm
  #define f7_ufx64_to_d_asm __f7_ufx64_to_d_asm
  #define f7_sfx64_to_d_asm __f7_sfx64_to_d_asm
  #define f7_class_D_asm __f7_class_D_asm
--- 222,227 ----
diff -Nrcpad gcc-15-20260626/libgcc/config/avr/libf7/libf7-asm.sx gcc-15-20260703/libgcc/config/avr/libf7/libf7-asm.sx
*** gcc-15-20260626/libgcc/config/avr/libf7/libf7-asm.sx	Fri Jun 26 22:32:17 2026
--- gcc-15-20260703/libgcc/config/avr/libf7/libf7-asm.sx	Fri Jul  3 22:32:16 2026
*************** _DEFUN __fractdfusa
*** 2465,2512 ****
  _ENDF __fractdfusa
  #endif /* F7MOD_D2usa_ */
  
  
! #ifdef F7MOD_D2fx_
! ;;; Convert double R18 to a 64-bit fixed point value.
! ;;; R18 d_to_fx64 (double R18, int8_t fbit R16);
! ;;; |FBIT| accounts for the extra fbits compared to [u]int64_t.
! ;;; FBIT < 0 indicates a signed conversion.
! ;;; FBIT > 0 indicates an unsigned conversion.
! DEFUN d_to_fx64
!     do_prologue_saves  4, F7_SIZEOF
! 
!     ;; Y = FramePointer + 1
!     adiw    Y,      1
! 
!     ;; FP + 1 = (f7_t) arg
!     wmov    r16,    Y
! 
!     ;; Convert double R18 to f7_t *R16.
!     XCALL   F7_NAME (set_double_impl)
  
!     ;; Prepare for *R24 = ldexp (*R24, R22).  ldexp() accounts for the
!     ;; fractional bits of the fixed point value, i.e. we have to <<= FBIT.
!     wmov    r24,    r16
!     ;; Zero-extend FBIT.
!     clr     r23
!     ;; R16 has been clobbered.  Fetch it from where prologue_saves put it.
!     ldd     r22,    Y + F7_SIZEOF + 3       ; Saved R16
!     tst     r22
!     brmi 1f
  
!     ;; Positive FBIT indicates an unsigned conversion.
!     XCALL   F7_NAME (Ildexp)
!     XCALL   F7_NAME (get_u64)
!     rjmp 9f
  
! 1:  ;; Negative FBIT indicates a signed conversion.
!     neg     r22                 ; FBIT := |FBIT|
!     XCALL   F7_NAME (Ildexp)
!     XCALL   F7_NAME (get_s64)
  
! 9:  do_epilogue_restores  4, F7_SIZEOF
! ENDF d_to_fx64
! #endif /* F7MOD_D2fx_ */
  
  
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
--- 2465,2520 ----
  _ENDF __fractdfusa
  #endif /* F7MOD_D2usa_ */
  
+ #ifdef F7MOD_D2da_
+ _DEFUN __fractdfda
+     ;; Multiply with 2^FBIT to get a DA result in r25:r18.
+     subi    r24, dex_lo (-__DA_FBIT__)
+     sbci    r25, dex_hi (-__DA_FBIT__)
+     XJMP    __fixdfdi
+ _ENDF __fractdfda
+ #endif /* F7MOD_D2da_ */
  
! #ifdef F7MOD_D2uda_
! _DEFUN __fractdfuda
!     ;; Multiply with 2^FBIT to get an UDA result in r25:r18.
!     subi    r25, dex_hi (-__UDA_FBIT__)
!     XJMP    __fixunsdfdi
! _ENDF __fractdfuda
! #endif /* F7MOD_D2uda_ */
  
! #ifdef F7MOD_D2ta_
! _DEFUN __fractdfta
!     ;; Multiply with 2^FBIT to get a TA result in r25:r18.
!     subi    r24, dex_lo (-__TA_FBIT__)
!     sbci    r25, dex_hi (-__TA_FBIT__)
!     XJMP    __fixdfdi
! _ENDF __fractdfta
! #endif /* F7MOD_D2ta_ */
  
! #ifdef F7MOD_D2uta_
! _DEFUN __fractdfuta
!     ;; Multiply with 2^FBIT to get an UTA result in r25:r18.
!     subi    r25, dex_hi (-__UTA_FBIT__)
!     XJMP    __fixunsdfdi
! _ENDF __fractdfuta
! #endif /* F7MOD_D2uta_ */
  
! #ifdef F7MOD_D2dq_
! _DEFUN __fractdfdq
!     ;; Multiply with 2^FBIT to get a DQ result in r25:r18.
!     subi    r24, dex_lo (-__DQ_FBIT__)
!     sbci    r25, dex_hi (-__DQ_FBIT__)
!     XJMP    __fixdfdi
! _ENDF __fractdfdq
! #endif /* F7MOD_D2dq_ */
  
! #ifdef F7MOD_D2udq_
! _DEFUN __fractdfudq
!     ;; Multiply with 2^FBIT to get an UDQ result in r25:r18.
!     subi    r25, dex_hi (-__UDQ_FBIT__)
!     XJMP    __fixunsdfdi
! _ENDF __fractdfudq
! #endif /* F7MOD_D2udq_ */
  
  
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff -Nrcpad gcc-15-20260626/libgcc/config/avr/libf7/libf7-common.mk gcc-15-20260703/libgcc/config/avr/libf7/libf7-common.mk
*** gcc-15-20260626/libgcc/config/avr/libf7/libf7-common.mk	Fri Jun 26 22:32:17 2026
--- gcc-15-20260703/libgcc/config/avr/libf7/libf7-common.mk	Fri Jul  3 22:32:16 2026
*************** F7_ASM_PARTS +=            ha2D uha2D sa
*** 34,42 ****
  F7_ASM_PARTS += fx2D
  
  # Double -> fixed-point conversions
! F7_ASM_PARTS += D2qq D2uqq D2hq D2uhq
! F7_ASM_PARTS +=            D2ha D2uha D2sa D2usa
! F7_ASM_PARTS += D2fx
  
  # Integer -> double conversions
  F7_ASM_PARTS += D_floatsidf D_floatunsidf
--- 34,41 ----
  F7_ASM_PARTS += fx2D
  
  # Double -> fixed-point conversions
! F7_ASM_PARTS += D2qq D2uqq D2hq D2uhq            D2dq D2udq
! F7_ASM_PARTS +=            D2ha D2uha D2sa D2usa D2da D2uda D2ta D2uta
  
  # Integer -> double conversions
  F7_ASM_PARTS += D_floatsidf D_floatunsidf
*************** F7F_asm += set_u64 set_s64 addsub_mant_s
*** 109,115 ****
  F7F_asm += to_integer to_unsigned clr_mant_lsbs
  F7F_asm += div sqrt_approx sqrt16_round sqrt16_floor
  F7F_asm += lshrdi3 ashldi3
! F7F_asm += d_to_fx64 ufx64_to_d sfx64_to_d
  F7F_asm += class_D
  
  F7F_asm += call_ddd call_xdd call_ddx
--- 108,114 ----
  F7F_asm += to_integer to_unsigned clr_mant_lsbs
  F7F_asm += div sqrt_approx sqrt16_round sqrt16_floor
  F7F_asm += lshrdi3 ashldi3
! F7F_asm += ufx64_to_d sfx64_to_d
  F7F_asm += class_D
  
  F7F_asm += call_ddd call_xdd call_ddx
diff -Nrcpad gcc-15-20260626/libgcc/config/avr/libf7/libf7.c gcc-15-20260703/libgcc/config/avr/libf7/libf7.c
*** gcc-15-20260626/libgcc/config/avr/libf7/libf7.c	Fri Jun 26 22:32:17 2026
--- gcc-15-20260703/libgcc/config/avr/libf7/libf7.c	Fri Jul  3 22:32:16 2026
*************** f7_double_t __floatdidf (int64_t x)
*** 140,197 ****
  #endif // F7MOD_floatdidf_
  
  
- extern uint64_t d_to_ufx (f7_double_t, int8_t) F7ASM(f7_d_to_fx64_asm);
- extern int64_t  d_to_sfx (f7_double_t, int8_t) F7ASM(f7_d_to_fx64_asm);
- 
- #ifdef F7MOD_fractdfda_
- F7_WEAK
- int64_t __fractdfda (f7_double_t d)
- {
-   return d_to_sfx (d, -__DA_FBIT__);
- }
- #endif // F7MOD_fractdfda_
- 
- #ifdef F7MOD_fractdfuda_
- F7_WEAK
- uint64_t __fractdfuda (f7_double_t d)
- {
-   return d_to_ufx (d, __UDA_FBIT__);
- }
- #endif // F7MOD_fractdfuda_
- 
- #ifdef F7MOD_fractdfta_
- F7_WEAK
- int64_t __fractdfta (f7_double_t d)
- {
-   return d_to_sfx (d, -__TA_FBIT__);
- }
- #endif // F7MOD_fractdfta_
- 
- #ifdef F7MOD_fractdfuta_
- F7_WEAK
- uint64_t __fractdfuta (f7_double_t d)
- {
-   return d_to_ufx (d, __UTA_FBIT__);
- }
- #endif // F7MOD_fractdfuta_
- 
- #ifdef F7MOD_fractdfdq_
- F7_WEAK
- int64_t __fractdfdq (f7_double_t d)
- {
-   return d_to_sfx (d, -__DQ_FBIT__);
- }
- #endif // F7MOD_fractdfdq_
- 
- #ifdef F7MOD_fractdfudq_
- F7_WEAK
- uint64_t __fractdfudq (f7_double_t d)
- {
-   return d_to_ufx (d, __UDQ_FBIT__);
- }
- #endif // F7MOD_fractdfudq_
- 
- 
  #ifdef F7MOD_init_
  f7_t* f7_init_impl (uint64_t mant, uint8_t flags, f7_t *cc, int16_t expo)
  {
--- 140,145 ----
diff -Nrcpad gcc-15-20260626/libgcc/config/avr/libf7/t-libf7 gcc-15-20260703/libgcc/config/avr/libf7/t-libf7
*** gcc-15-20260626/libgcc/config/avr/libf7/t-libf7	Fri Jun 26 22:32:17 2026
--- gcc-15-20260703/libgcc/config/avr/libf7/t-libf7	Fri Jul  3 22:32:16 2026
*************** F7_PREFIX = __f7_
*** 9,16 ****
  include $(libf7)/libf7-common.mk
  
  LIBF7_DF_CONV +=  floatundidf floatdidf # floatunsidf floatsidf
- LIBF7_DF_CONV +=  fractdfda fractdfta fractdfdq
- LIBF7_DF_CONV +=  fractdfuda fractdfuta fractdfudq
  
  # Wrappers like f7_lt_impl for f7_lt etc. because the latter is inline.
  LIBF7_DF_CMP  += lt le gt ge ne eq unord
--- 9,14 ----
diff -Nrcpad gcc-15-20260626/libstdc++-v3/ChangeLog gcc-15-20260703/libstdc++-v3/ChangeLog
*** gcc-15-20260626/libstdc++-v3/ChangeLog	Fri Jun 26 22:32:19 2026
--- gcc-15-20260703/libstdc++-v3/ChangeLog	Fri Jul  3 22:32:18 2026
***************
*** 1,3 ****
--- 1,32 ----
+ 2026-07-02  Yi Chen  <chencyy@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-07-01  Yi Chen  <chencyy@hygon.cn>
+ 
+ 	* src/c++11/random.cc (random_device::_M_init): Add signature_HYGON_ebx to
+ 	the RDSEED and RDRAND CPUID vendor allowlists.  For the default device on
+ 	Hygon, prefer RDRAND via a dedicated check at the top of the function.
+ 
+ 2026-07-02  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-25  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/125956
+ 	* src/c++20/format.cc [_GLIBCXX_HAVE_ICONV] (iconv_input): New
+ 	concept.
+ 	(__encoding::conv) [_GLIBCXX_HAVE_ICONV]: Use iconv_input to
+ 	decide which type to cast the input pointer to.
+ 
+ 2026-07-02  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-24  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/118158
+ 	* testsuite/27_io/filesystem/operations/pr118158.cc: Add
+ 	dg-require-mkfifo.
+ 
  2026-06-25  Jakub Jelinek  <jakub@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260626/libstdc++-v3/src/c++11/random.cc gcc-15-20260703/libstdc++-v3/src/c++11/random.cc
*** gcc-15-20260626/libstdc++-v3/src/c++11/random.cc	Fri Jun 26 22:32:19 2026
--- gcc-15-20260703/libstdc++-v3/src/c++11/random.cc	Fri Jul  3 22:32:18 2026
*************** namespace std _GLIBCXX_VISIBILITY(defaul
*** 390,403 ****
      }
  #endif // _GLIBCXX_USE_CRT_RAND_S
  
  #ifdef USE_RDSEED
      if (which & rdseed)
      {
        unsigned int eax, ebx, ecx, edx;
        // Check availability of cpuid and, for now at least, also the
!       // CPU signature for Intel and AMD.
        if (__get_cpuid_max(0, &ebx) > 0
! 	  && (ebx == signature_INTEL_ebx || ebx == signature_AMD_ebx))
  	{
  	  // CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18]
  	  __cpuid_count(7, 0, eax, ebx, ecx, edx);
--- 390,424 ----
      }
  #endif // _GLIBCXX_USE_CRT_RAND_S
  
+ #ifdef USE_RDRAND
+     // For the default device on Hygon prefer RDRAND (faster than RDSEED for
+     // bulk generation); an explicit "rdseed" token still selects rdseed below.
+     if (which == any)
+     {
+       unsigned int eax, ebx, ecx, edx;
+       if (__get_cpuid_max(0, &ebx) > 0 && ebx == signature_HYGON_ebx)
+ 	{
+ 	  // CPUID.01H:ECX.RDRAND[bit 30]
+ 	  __cpuid(1, eax, ebx, ecx, edx);
+ 	  if (ecx & bit_RDRND)
+ 	    {
+ 	      _M_func = &__x86_rdrand;
+ 	      return;
+ 	    }
+ 	}
+     }
+ #endif // USE_RDRAND
+ 
  #ifdef USE_RDSEED
      if (which & rdseed)
      {
        unsigned int eax, ebx, ecx, edx;
        // Check availability of cpuid and, for now at least, also the
!       // CPU signature for Intel, AMD and Hygon.
        if (__get_cpuid_max(0, &ebx) > 0
! 	  && (ebx == signature_INTEL_ebx
! 	      || ebx == signature_AMD_ebx
! 	      || ebx == signature_HYGON_ebx))
  	{
  	  // CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18]
  	  __cpuid_count(7, 0, eax, ebx, ecx, edx);
*************** namespace std _GLIBCXX_VISIBILITY(defaul
*** 425,433 ****
      {
        unsigned int eax, ebx, ecx, edx;
        // Check availability of cpuid and, for now at least, also the
!       // CPU signature for Intel and AMD.
        if (__get_cpuid_max(0, &ebx) > 0
! 	  && (ebx == signature_INTEL_ebx || ebx == signature_AMD_ebx))
  	{
  	  // CPUID.01H:ECX.RDRAND[bit 30]
  	  __cpuid(1, eax, ebx, ecx, edx);
--- 446,456 ----
      {
        unsigned int eax, ebx, ecx, edx;
        // Check availability of cpuid and, for now at least, also the
!       // CPU signature for Intel, AMD and Hygon.
        if (__get_cpuid_max(0, &ebx) > 0
! 	  && (ebx == signature_INTEL_ebx
! 	      || ebx == signature_AMD_ebx
! 	      || ebx == signature_HYGON_ebx))
  	{
  	  // CPUID.01H:ECX.RDRAND[bit 30]
  	  __cpuid(1, eax, ebx, ecx, edx);
diff -Nrcpad gcc-15-20260626/libstdc++-v3/src/c++20/format.cc gcc-15-20260703/libstdc++-v3/src/c++20/format.cc
*** gcc-15-20260626/libstdc++-v3/src/c++20/format.cc	Fri Jun 26 22:32:19 2026
--- gcc-15-20260703/libstdc++-v3/src/c++20/format.cc	Fri Jul  3 22:32:18 2026
*************** struct mutex
*** 58,63 ****
--- 58,72 ----
  };
  #endif
  
+ #ifdef _GLIBCXX_HAVE_ICONV
+ // Detect whether type T* can be used as the second argument to iconv.
+ // SUSv2 used 'const char**', but POSIX.1-2003 uses 'char**'.
+ template<typename T>
+   concept iconv_input = requires (::iconv_t cd, T in, size_t n, char** out) {
+     ::iconv(cd, &in, &n, out, &n);
+   };
+ #endif
+ 
  // A non-standard locale::facet that caches the locale's std::text_encoding
  // and an iconv descriptor for converting from that encoding to UTF-8.
  struct __encoding : locale::facet
*************** struct __encoding : locale::facet
*** 111,118 ****
      bool done = false;
  
      auto overwrite = [&](char* p, size_t n) {
        auto inbytes
! 	= const_cast<char*>(input.data()) + input.size() - inbytesleft;
        char* outbytes = p + written;
        size_t outbytesleft = n - written;
        size_t res = ::iconv(_M_cd, &inbytes, &inbytesleft,
--- 120,128 ----
      bool done = false;
  
      auto overwrite = [&](char* p, size_t n) {
+       using input_t = __conditional_t<iconv_input<char*>, char*, const char*>;
        auto inbytes
! 	= const_cast<input_t>(input.data()) + input.size() - inbytesleft;
        char* outbytes = p + written;
        size_t outbytesleft = n - written;
        size_t res = ::iconv(_M_cd, &inbytes, &inbytesleft,
diff -Nrcpad gcc-15-20260626/libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc gcc-15-20260703/libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc
*** gcc-15-20260626/libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc	Fri Jun 26 22:32:20 2026
--- gcc-15-20260703/libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc	Fri Jul  3 22:32:19 2026
***************
*** 1,5 ****
--- 1,6 ----
  // { dg-do run { target c++17 } }
  // { dg-require-filesystem-ts "" }
+ // { dg-require-mkfifo "" }
  
  #include <filesystem>
  #include <testsuite_fs.h>
