diff -Nrcpad gcc-14-20260528/LAST_UPDATED gcc-14-20260604/LAST_UPDATED
*** gcc-14-20260528/LAST_UPDATED	Thu May 28 22:32:17 2026
--- gcc-14-20260604/LAST_UPDATED	Thu Jun  4 22:32:21 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-14 revision 1f3d68b71ce855ec2e63d4f7718939b9489930c0
--- 1 ----
! Obtained from git: releases/gcc-14 revision 850cef3261fd6cf9b76250338d1e123ef7b3d0cb
diff -Nrcpad gcc-14-20260528/MD5SUMS gcc-14-20260604/MD5SUMS
*** gcc-14-20260528/MD5SUMS	Thu May 28 22:32:21 2026
--- gcc-14-20260604/MD5SUMS	Thu Jun  4 22:32:25 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20260528.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20260604.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** fc9280b02bc68e4fb1ef8d51ccc25061  Change
*** 23,29 ****
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! 05a80d05faa6545d73937da917fc84c7  LAST_UPDATED
  1671040823f8eb8436a06fdd18065e02  MAINTAINERS
  304c3887135aefa27c21292ec585b0a3  Makefile.def
  8dd93fbf2e32bcbd2faba10e3b8ba2b0  Makefile.in
--- 23,29 ----
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! 74494b2ba05a22397ac999a7ef822af9  LAST_UPDATED
  1671040823f8eb8436a06fdd18065e02  MAINTAINERS
  304c3887135aefa27c21292ec585b0a3  Makefile.def
  8dd93fbf2e32bcbd2faba10e3b8ba2b0  Makefile.in
*************** bc7394806417778d77541ba1ec0e4a70  gcc/BA
*** 505,511 ****
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! abe3d48bd4f8ee6aba9507a54cbc4aa3  gcc/ChangeLog
  a3b63c675afa7a655cc2bfa8a907af79  gcc/ChangeLog-1997
  d9a88529352a010253c2e8fb1ed6023b  gcc/ChangeLog-1998
  240f08f81cb4699e8b49347db38233db  gcc/ChangeLog-1999
--- 505,511 ----
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! eb92160f3579cd09a89b70c10506647e  gcc/ChangeLog
  a3b63c675afa7a655cc2bfa8a907af79  gcc/ChangeLog-1997
  d9a88529352a010253c2e8fb1ed6023b  gcc/ChangeLog-1998
  240f08f81cb4699e8b49347db38233db  gcc/ChangeLog-1999
*************** fb3fadb88e1d2b3b640cfaaa5ff11780  gcc/Ch
*** 541,547 ****
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! 211ee267ba0da5486b7341c60383741b  gcc/DATESTAMP
  d41d8cd98f00b204e9800998ecf8427e  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
--- 541,547 ----
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! 35e5b002c0f21c6f27678761beac11b5  gcc/DATESTAMP
  d41d8cd98f00b204e9800998ecf8427e  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
*************** cc68db36c7e26368cce1af309ad2308d  gcc/co
*** 4274,4280 ****
  a9d1d80c40cc6eb8e9a32d54f82dae43  gcc/config/lm32/t-lm32
  660559cdac2b08e91486a9db7b4a2872  gcc/config/lm32/t-rtems
  ddefbf04240463de3ebe735c18bd3da8  gcc/config/lm32/uclinux-elf.h
! 8ed53c8d6e2ffd1c4348b1509c392da9  gcc/config/loongarch/constraints.md
  d4a731bdf01a61d063fe5c12e0ae15a3  gcc/config/loongarch/elf.h
  17e35e205e8d128d6658e239c7abcee0  gcc/config/loongarch/generic.md
  287b403c9c4fcd7872ffc302707dd8e0  gcc/config/loongarch/genopts/gen-evolution.awk
--- 4274,4280 ----
  a9d1d80c40cc6eb8e9a32d54f82dae43  gcc/config/lm32/t-lm32
  660559cdac2b08e91486a9db7b4a2872  gcc/config/lm32/t-rtems
  ddefbf04240463de3ebe735c18bd3da8  gcc/config/lm32/uclinux-elf.h
! c940b279543e17d86f4d1fad1fead150  gcc/config/loongarch/constraints.md
  d4a731bdf01a61d063fe5c12e0ae15a3  gcc/config/loongarch/elf.h
  17e35e205e8d128d6658e239c7abcee0  gcc/config/loongarch/generic.md
  287b403c9c4fcd7872ffc302707dd8e0  gcc/config/loongarch/genopts/gen-evolution.awk
*************** fc08ad18c12daeb6c459e9a5da085d02  gcc/co
*** 4305,4322 ****
  e79a168e4a8c0322a884b11ed18cf218  gcc/config/loongarch/loongarch-modes.def
  ea6cc43b3fa3313db4228947eed2152e  gcc/config/loongarch/loongarch-opts.cc
  8869aeb1ace55d4ee67306c723b6069c  gcc/config/loongarch/loongarch-opts.h
! 3ce5af4b5c069929ba519548d5342e90  gcc/config/loongarch/loongarch-protos.h
  3b7b410fd2ede1c56c692fa390a8d415  gcc/config/loongarch/loongarch-str.h
  2088d1b3164d3464806a7627d2fd6e52  gcc/config/loongarch/loongarch-tune.h
! a2c77447e497eb94952bc52b487bf6f2  gcc/config/loongarch/loongarch.cc
  39c8662694bff1c4d52f90cba43e5048  gcc/config/loongarch/loongarch.h
! 2bf401adae6dfb1d853a71961fec58c9  gcc/config/loongarch/loongarch.md
  b62396c60e7bd1b4de8956c5869d45f2  gcc/config/loongarch/loongarch.opt
  93b3f21362e888da73ecb40a067439a3  gcc/config/loongarch/loongarch.opt.urls
  f3b13e309145e71b5771549c999f0df8  gcc/config/loongarch/lsx.md
  936e07cd1770c2a1e09db72cf3dc7e24  gcc/config/loongarch/lsxintrin.h
  42270d3318bceb069807243f3475a89f  gcc/config/loongarch/musl.h
! 0dd8001c6f7ca137d2ba02e96b0f3933  gcc/config/loongarch/predicates.md
  364fcf413b94f515b05526691d52c093  gcc/config/loongarch/simd.md
  f4de53ee085303195a3c4eb57c3663c6  gcc/config/loongarch/sync.md
  49279b28d5c2ec9c67b9f93840713af2  gcc/config/loongarch/t-linux
--- 4305,4322 ----
  e79a168e4a8c0322a884b11ed18cf218  gcc/config/loongarch/loongarch-modes.def
  ea6cc43b3fa3313db4228947eed2152e  gcc/config/loongarch/loongarch-opts.cc
  8869aeb1ace55d4ee67306c723b6069c  gcc/config/loongarch/loongarch-opts.h
! 00ec93cdb09ba7cbb6eeed05ad292f03  gcc/config/loongarch/loongarch-protos.h
  3b7b410fd2ede1c56c692fa390a8d415  gcc/config/loongarch/loongarch-str.h
  2088d1b3164d3464806a7627d2fd6e52  gcc/config/loongarch/loongarch-tune.h
! 93afbeb9657e1e644e672b25f99dcdd0  gcc/config/loongarch/loongarch.cc
  39c8662694bff1c4d52f90cba43e5048  gcc/config/loongarch/loongarch.h
! 9b56672053666990c82dd3985546af27  gcc/config/loongarch/loongarch.md
  b62396c60e7bd1b4de8956c5869d45f2  gcc/config/loongarch/loongarch.opt
  93b3f21362e888da73ecb40a067439a3  gcc/config/loongarch/loongarch.opt.urls
  f3b13e309145e71b5771549c999f0df8  gcc/config/loongarch/lsx.md
  936e07cd1770c2a1e09db72cf3dc7e24  gcc/config/loongarch/lsxintrin.h
  42270d3318bceb069807243f3475a89f  gcc/config/loongarch/musl.h
! 2310092ffd3bc6f9c3f464550955a217  gcc/config/loongarch/predicates.md
  364fcf413b94f515b05526691d52c093  gcc/config/loongarch/simd.md
  f4de53ee085303195a3c4eb57c3663c6  gcc/config/loongarch/sync.md
  49279b28d5c2ec9c67b9f93840713af2  gcc/config/loongarch/t-linux
*************** b7669cc185ce4e8fa5543db9fc552fad  gcc/co
*** 4726,4734 ****
  961575276a4c92065805fa132d6f96a1  gcc/config/pa/pa-openbsd.h
  9a661bb63af8309862f216a5145b35ff  gcc/config/pa/pa-opts.h
  1ab2b014b27f77e96f50795bfab8fcbd  gcc/config/pa/pa-protos.h
! 01111c68d97e57d1049b7ce4fefaca05  gcc/config/pa/pa.cc
  3508830133b8a3222d8b89317c41049e  gcc/config/pa/pa.h
! ca71709340d554f30a50c48b53a9aecd  gcc/config/pa/pa.md
  99a0932bde9ea4de72d6b9b3cb2b2d99  gcc/config/pa/pa.opt
  8cc2f0b358c76ec2ce7a16d18a9ecdab  gcc/config/pa/pa.opt.urls
  2a4bf2e386b22bab714abdf5f5712158  gcc/config/pa/pa32-linux.h
--- 4726,4734 ----
  961575276a4c92065805fa132d6f96a1  gcc/config/pa/pa-openbsd.h
  9a661bb63af8309862f216a5145b35ff  gcc/config/pa/pa-opts.h
  1ab2b014b27f77e96f50795bfab8fcbd  gcc/config/pa/pa-protos.h
! 57578a85112a6e0776ce46118490e479  gcc/config/pa/pa.cc
  3508830133b8a3222d8b89317c41049e  gcc/config/pa/pa.h
! fa6810d2de88cd926ba35e2e5954565d  gcc/config/pa/pa.md
  99a0932bde9ea4de72d6b9b3cb2b2d99  gcc/config/pa/pa.opt
  8cc2f0b358c76ec2ce7a16d18a9ecdab  gcc/config/pa/pa.opt.urls
  2a4bf2e386b22bab714abdf5f5712158  gcc/config/pa/pa32-linux.h
*************** e8a9eb01b9451a357155e7152df1c669  gcc/ta
*** 8062,8068 ****
  a05663c52c607143c607d3ecf1391979  gcc/targhooks.cc
  51d240e574a3f9ecec346d64a04ac634  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! c4496be519fa2e882352bbdeee54c2cf  gcc/testsuite/ChangeLog
  862f04afbd87da2cc6bc432c3f28430f  gcc/testsuite/ChangeLog-1993-2007
  029a5d8dacd25eb5d4711452ac448e5b  gcc/testsuite/ChangeLog-2008
  13ac28c41d51b66b4ec40dba6bd50f39  gcc/testsuite/ChangeLog-2009
--- 8062,8068 ----
  a05663c52c607143c607d3ecf1391979  gcc/targhooks.cc
  51d240e574a3f9ecec346d64a04ac634  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! 52ec024c73c0f2d47d8403f7f0adce16  gcc/testsuite/ChangeLog
  862f04afbd87da2cc6bc432c3f28430f  gcc/testsuite/ChangeLog-1993-2007
  029a5d8dacd25eb5d4711452ac448e5b  gcc/testsuite/ChangeLog-2008
  13ac28c41d51b66b4ec40dba6bd50f39  gcc/testsuite/ChangeLog-2009
*************** acf1fac916847c2064b8d2bbb6535828  gcc/te
*** 78687,78692 ****
--- 78687,78693 ----
  51927631f78916e06162754b5c3d24fd  gcc/testsuite/gcc.target/loongarch/pr122097.c
  0626ac54385b7d00394be7a0b09850a1  gcc/testsuite/gcc.target/loongarch/pr122695-1.c
  fb640df1e5eb969859e5c360f608dec4  gcc/testsuite/gcc.target/loongarch/pr122695-2.c
+ 8784ee3164375854ef7b1ffc0c536b5e  gcc/testsuite/gcc.target/loongarch/pr125049.c
  3adba2a8ae6f671eb22ec8228777c1ac  gcc/testsuite/gcc.target/loongarch/prolog-opt.c
  1bfa30f99dc5f04f569fbff68640ab19  gcc/testsuite/gcc.target/loongarch/recip-divf.c
  dfa82d46bae04856dd91309f03684574  gcc/testsuite/gcc.target/loongarch/recip-sqrtf.c
diff -Nrcpad gcc-14-20260528/gcc/ChangeLog gcc-14-20260604/gcc/ChangeLog
*** gcc-14-20260528/gcc/ChangeLog	Thu May 28 22:32:04 2026
--- gcc-14-20260604/gcc/ChangeLog	Thu Jun  4 22:32:05 2026
***************
*** 1,3 ****
--- 1,43 ----
+ 2026-06-03  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2026-05-08  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	PR target/125049
+ 	* config/loongarch/predicates.md (ssp_operand): New
+ 	define_predicate.
+ 	(ssp_normal_operand): New define_predicate.
+ 	* config/loongarch/constraints.md (ZE): New define_constraint.
+ 	(ZF): New define_constraint.
+ 	* config/loongarch/loongarch.md (UNSPEC_SSP): New unspec.
+ 	(cbranch4): Add "@" to create gen_cbranch4(machine_mode, ...).
+ 	(@stack_protect_combined_set_normal_<mode>): New define_insn.
+ 	(@stack_protect_combined_set_extreme_<mode>): New define_insn.
+ 	(@stack_protect_combined_test_internal_<mode>): New define_insn.
+ 	(stack_protect_combined_set): New define_expand.
+ 	(stack_protect_combined_test): New define_expand.
+ 	* config/loongarch/loongarch-protos.h
+ 	(loongarch_output_asm_load_canary): Declare.
+ 	* config/loongarch/loongarch.cc (loongarch_print_operand): Allow
+ 	'v' to print d/w for DImode/SImode.
+ 	(loongarch_output_asm_load_canary): Implement.
+ 
+ 2026-06-01  John David Anglin  <danglin@gcc.gnu.org>
+ 
+ 	* config/pa/pa.cc (pa_trampoline_init): Rework to use
+ 	clear_cache pattern.
+ 	* config/pa/pa.md (dcacheflush): Use "<<" condition instead
+ 	of "<<=".
+ 	(icacheflush): Remove.
+ 	(icacheflush1, icacheflush2, icacheflush3): New flush patterns
+ 	for PA 1.x targets, PA 2.0 targets, and PA 1.x no space
+ 	register targets.
+ 	(clear_cache): Rework to flush data and instruction caches.
+ 	Skip flush if the start address is greater than or equal to
+ 	the end address.  Don't align the end address to a cacheline
+ 	boundary.  Handle instruction flushes for PA 1.x targets,
+ 	PA 2.0 targets, and PA 1.x no space register targets.
+ 
  2026-05-25  Georg-Johann Lay  <avr@gjlay.de>
  
  	Backported from master:
diff -Nrcpad gcc-14-20260528/gcc/DATESTAMP gcc-14-20260604/gcc/DATESTAMP
*** gcc-14-20260528/gcc/DATESTAMP	Thu May 28 22:32:05 2026
--- gcc-14-20260604/gcc/DATESTAMP	Thu Jun  4 22:32:05 2026
***************
*** 1 ****
! 20260528
--- 1 ----
! 20260604
diff -Nrcpad gcc-14-20260528/gcc/config/loongarch/constraints.md gcc-14-20260604/gcc/config/loongarch/constraints.md
*** gcc-14-20260528/gcc/config/loongarch/constraints.md	Thu May 28 22:32:05 2026
--- gcc-14-20260604/gcc/config/loongarch/constraints.md	Thu Jun  4 22:32:06 2026
***************
*** 365,367 ****
--- 365,376 ----
     and offset that is suitable for use in instructions with the same
     addressing mode as @code{preld}."
     (match_test "loongarch_12bit_offset_address_p (op, mode)"))
+ 
+ (define_constraint "ZE"
+   "A symbolic suitable as stack canary in the normal/medium code model."
+   (match_operand 0 "ssp_normal_operand"))
+ 
+ (define_constraint "ZF"
+   "A symbolic suitable as stack canary, but in the extreme code model."
+   (and (match_operand 0 "ssp_operand")
+        (not (match_operand 0 "ssp_normal_operand"))))
diff -Nrcpad gcc-14-20260528/gcc/config/loongarch/loongarch-protos.h gcc-14-20260604/gcc/config/loongarch/loongarch-protos.h
*** gcc-14-20260528/gcc/config/loongarch/loongarch-protos.h	Thu May 28 22:32:06 2026
--- gcc-14-20260604/gcc/config/loongarch/loongarch-protos.h	Thu Jun  4 22:32:06 2026
*************** extern void loongarch_emit_swrsqrtsf (rt
*** 215,218 ****
--- 215,219 ----
  extern void loongarch_emit_swdivsf (rtx, rtx, rtx, machine_mode);
  extern bool loongarch_explicit_relocs_p (enum loongarch_symbol_type);
  extern bool loongarch_symbol_extreme_p (enum loongarch_symbol_type);
+ extern void loongarch_output_asm_load_canary (rtx reg, rtx canary, rtx tmp);
  #endif /* ! GCC_LOONGARCH_PROTOS_H */
diff -Nrcpad gcc-14-20260528/gcc/config/loongarch/loongarch.cc gcc-14-20260604/gcc/config/loongarch/loongarch.cc
*** gcc-14-20260528/gcc/config/loongarch/loongarch.cc	Thu May 28 22:32:06 2026
--- gcc-14-20260604/gcc/config/loongarch/loongarch.cc	Thu Jun  4 22:32:06 2026
*************** loongarch_print_operand (FILE *file, rtx
*** 6372,6383 ****
--- 6372,6385 ----
  	case E_V4SFmode:
  	case E_V8SImode:
  	case E_V8SFmode:
+ 	case E_SImode:
  	  fprintf (file, "w");
  	  break;
  	case E_V2DImode:
  	case E_V2DFmode:
  	case E_V4DImode:
  	case E_V4DFmode:
+ 	case E_DImode:
  	  fprintf (file, "d");
  	  break;
  	default:
*************** loongarch_compute_pressure_classes (reg_
*** 10921,10926 ****
--- 10923,10977 ----
    return i;
  }
  
+ /* Output assembly to materialize the address of the stack canary value
+    into reg.  The third argument, tmp, should be and should only be
+    non-NULL if the extreme code model is effective for the canary.  If
+    the fourth arugment, load, is true, the canary value is loaded into
+    the register.
+ 
+    The assembly cannot be splitted due to security reason.  */
+ void
+ loongarch_output_asm_load_canary (rtx reg, rtx canary, rtx tmp)
+ {
+   gcc_checking_assert (ssp_operand (canary, VOIDmode));
+   gcc_checking_assert ((!tmp) == ssp_normal_operand (canary, VOIDmode));
+   gcc_checking_assert (register_operand (reg, Pmode));
+ 
+   rtx op[] = {reg, canary, tmp};
+   bool got = (loongarch_classify_symbol (canary) == SYMBOL_GOT_DISP);
+   bool need_ld = false;
+ 
+   if (la_opt_explicit_relocs != EXPLICIT_RELOCS_ALWAYS)
+     {
+       if (got)
+ 	output_asm_insn (tmp ? "la.global\t%0,%2,%1" : "la.global\t%0,%1",
+ 			 op);
+       else
+ 	output_asm_insn (tmp ? "la.local\t%0,%2,%1" : "la.local\t%0,%1",
+ 			 op);
+ 
+       need_ld = true;
+     }
+   else
+     {
+       output_asm_insn ("pcalau12i\t%0,%r1", op);
+       if (!tmp)
+ 	output_asm_insn ("ld.%v0\t%0,%0,%L1", op);
+       else
+ 	{
+ 	  output_asm_insn ("addi.d\t%2,$r0,%L1", op);
+ 	  output_asm_insn ("lu32i.d\t%2,%R1", op);
+ 	  output_asm_insn ("lu52i.d\t%2,%2,%H1", op);
+ 	  output_asm_insn ("ldx.d\t%0,%0,%2", op);
+ 	}
+ 
+       need_ld = got;
+     }
+ 
+   if (need_ld)
+     output_asm_insn ("ld.%v0\t%0,%0,0", op);
+ }
+ 
  /* Initialize the GCC target structure.  */
  #undef TARGET_ASM_ALIGNED_HI_OP
  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
diff -Nrcpad gcc-14-20260528/gcc/config/loongarch/loongarch.md gcc-14-20260604/gcc/config/loongarch/loongarch.md
*** gcc-14-20260528/gcc/config/loongarch/loongarch.md	Thu May 28 22:32:06 2026
--- gcc-14-20260604/gcc/config/loongarch/loongarch.md	Thu Jun  4 22:32:06 2026
***************
*** 88,93 ****
--- 88,95 ----
    UNSPEC_LOAD_SYMBOL_OFFSET64
    UNSPEC_LA_PCREL_64_PART1
    UNSPEC_LA_PCREL_64_PART2
+ 
+   UNSPEC_SSP
  ])
  
  (define_c_enum "unspecv" [
***************
*** 3340,3346 ****
  ;; QImode values so we can force zero-extension.
  (define_mode_iterator BR [(QI "TARGET_64BIT") SI (DI "TARGET_64BIT")])
  
! (define_expand "cbranch<mode>4"
    [(set (pc)
  	(if_then_else (match_operator 0 "comparison_operator"
  			[(match_operand:BR 1 "register_operand")
--- 3342,3348 ----
  ;; QImode values so we can force zero-extension.
  (define_mode_iterator BR [(QI "TARGET_64BIT") SI (DI "TARGET_64BIT")])
  
! (define_expand "@cbranch<mode>4"
    [(set (pc)
  	(if_then_else (match_operator 0 "comparison_operator"
  			[(match_operand:BR 1 "register_operand")
***************
*** 4386,4391 ****
--- 4388,4477 ----
      operands[0] = loongarch_rewrite_mem_for_simple_ldst (operands[0]);
    })
  
+ ;; Set and check against stack canary without leaving it in a register.
+ ;; DO NOT ATTEMPT TO SPLIT THESE INSNS!  It's important for security reason
+ ;; that the canary value does not live beyond the life of this sequence.
+ 
+ (define_insn "@stack_protect_combined_set_normal_<mode>"
+   [(set (match_operand:P 0 "memory_operand" "=m,ZC")
+         (unspec:P [(mem:P (match_operand:P 1 "ssp_normal_operand"))]
+ 		  UNSPEC_SSP))
+    (set (match_scratch:P 2 "=&r,&r") (const_int 0))]
+   ""
+ {
+   loongarch_output_asm_load_canary (operands[2], operands[1], NULL_RTX);
+   output_asm_insn (which_alternative ? "stptr.d\t%2,%0" : "st.d\t%2,%0",
+ 		   operands);
+   return "ori\t%2,$r0,0";
+ }
+   [(set_attr "type" "store")
+    (set_attr "length" "20")])
+ 
+ (define_insn "@stack_protect_combined_set_extreme_<mode>"
+   [(set (match_operand:P 0 "memory_operand" "=m,ZC")
+         (unspec:P [(mem:P (match_operand:P 1 "ssp_operand"))] UNSPEC_SSP))
+    (set (match_scratch:P 2 "=&r,&r") (const_int 0))
+    (set (match_scratch:P 3 "=&r,&r") (const_int 0))]
+   ""
+ {
+   loongarch_output_asm_load_canary (operands[2], operands[1], operands[3]);
+   output_asm_insn (which_alternative ? "stptr.d\t%2,%0" : "st.d\t%2,%0",
+ 		   operands);
+   return "ori\t%2,$r0,0\n\tori\t%3,$r0,0";
+ }
+   [(set_attr "type" "store")
+    (set_attr "length" "36")])
+ 
+ (define_insn "@stack_protect_combined_test_internal_<mode>"
+   [(set (match_operand:P 0 "register_operand" "=r,r,&r,&r")
+ 	(xor:P
+ 	  (match_operand:P 1 "memory_operand" "=m,ZC,m,ZC")
+ 	    (unspec:P
+ 	      [(mem:P (match_operand:P 2 "ssp_operand" "ZE,ZE,ZF,ZF"))]
+ 	      UNSPEC_SSP)))
+    (set (match_scratch:P 3 "=&r,&r,&r,&r") (const_int 0))]
+   ""
+ {
+   rtx t = (which_alternative >= 2 ? operands[0] : NULL_RTX);
+   loongarch_output_asm_load_canary (operands[3], operands[2], t);
+   output_asm_insn ((which_alternative & 1) ? "ldptr.d\t%0,%1"
+ 					   : "ld.d\t%0,%1",
+ 		   operands);
+   return "xor\t%0,%0,%3\n\tori\t%3,$r0,0";
+ }
+   [(set_attr "type" "load,load,load,load")
+    (set_attr "length" "24,24,36,36")])
+ 
+ (define_expand "stack_protect_combined_set"
+   [(match_operand 0 "memory_operand")
+    (match_operand 1 "memory_operand")]
+   ""
+ {
+   rtx canary = XEXP (operands[1], 0);
+   auto fn = (ssp_normal_operand (canary, VOIDmode)
+ 	     ? gen_stack_protect_combined_set_normal
+ 	     : gen_stack_protect_combined_set_extreme);
+ 
+   emit_insn (fn (Pmode, operands[0], canary));
+   DONE;
+ })
+ 
+ (define_expand "stack_protect_combined_test"
+   [(match_operand 0 "memory_operand")
+    (match_operand 1 "memory_operand")
+    (match_operand 2 "")]
+   ""
+ {
+   rtx t = gen_reg_rtx (Pmode);
+   rtx canary = XEXP (operands[1], 0);
+   emit_insn (gen_stack_protect_combined_test_internal (Pmode, t,
+ 						       operands[0],
+ 						       canary));
+   rtx cond = gen_rtx_EQ (VOIDmode, t, const0_rtx);
+   emit_jump_insn (gen_cbranch4 (Pmode, cond, t, const0_rtx, operands[2]));
+   DONE;
+ })
+ 
  ;; Synchronization instructions.
  
  (include "sync.md")
diff -Nrcpad gcc-14-20260528/gcc/config/loongarch/predicates.md gcc-14-20260604/gcc/config/loongarch/predicates.md
*** gcc-14-20260528/gcc/config/loongarch/predicates.md	Thu May 28 22:32:06 2026
--- gcc-14-20260604/gcc/config/loongarch/predicates.md	Thu Jun  4 22:32:06 2026
***************
*** 588,593 ****
--- 588,601 ----
   (ior (match_operand 0 "register_operand")
        (match_operand 0 "symbolic_off64_operand")))
  
+ ;; Currently stack canary must be the global symbol __stack_chk_guard.
+ (define_predicate "ssp_operand" (match_code "symbol_ref"))
+ 
+ ;; If the stack canary is within the normal/medium code model.
+ (define_predicate "ssp_normal_operand"
+   (and (match_operand 0 "ssp_operand")
+        (not (match_operand 0 "symbolic_off64_operand"))))
+ 
  (define_predicate "equality_operator"
    (match_code "eq,ne"))
  
diff -Nrcpad gcc-14-20260528/gcc/config/pa/pa.cc gcc-14-20260604/gcc/config/pa/pa.cc
*** gcc-14-20260528/gcc/config/pa/pa.cc	Thu May 28 22:32:06 2026
--- gcc-14-20260604/gcc/config/pa/pa.cc	Thu Jun  4 22:32:06 2026
*************** static void
*** 10624,10633 ****
  pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
  {
    rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
!   rtx start_addr = gen_reg_rtx (Pmode);
!   rtx end_addr = gen_reg_rtx (Pmode);
!   rtx line_length = gen_reg_rtx (Pmode);
!   rtx r_tramp, tmp;
  
    emit_block_move (m_tramp, assemble_trampoline_template (),
  		   GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
--- 10624,10630 ----
  pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
  {
    rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
!   rtx start, end, r_tramp, tmp;
  
    emit_block_move (m_tramp, assemble_trampoline_template (),
  		   GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
*************** pa_trampoline_init (rtx m_tramp, tree fn
*** 10635,10640 ****
--- 10632,10640 ----
  
    if (!TARGET_64BIT)
      {
+       /* Start of trampoline code.  */
+       start = r_tramp;
+ 
        tmp = adjust_address (m_tramp, Pmode, 48);
        emit_move_insn (tmp, fnaddr);
        tmp = adjust_address (m_tramp, Pmode, 52);
*************** pa_trampoline_init (rtx m_tramp, tree fn
*** 10642,10669 ****
  
        /* Create a fat pointer for the trampoline.  */
        tmp = adjust_address (m_tramp, Pmode, 56);
!       emit_move_insn (tmp, r_tramp);
        tmp = adjust_address (m_tramp, Pmode, 60);
        emit_move_insn (tmp, gen_rtx_REG (Pmode, 19));
- 
-       /* fdc and fic only use registers for the address to flush,
- 	 they do not accept integer displacements.  We align the
- 	 start and end addresses to the beginning of their respective
- 	 cache lines to minimize the number of lines flushed.  */
-       emit_insn (gen_andsi3 (start_addr, r_tramp,
- 			     GEN_INT (-MIN_CACHELINE_SIZE)));
-       tmp = force_reg (Pmode, plus_constant (Pmode, r_tramp,
- 					     TRAMPOLINE_CODE_SIZE-1));
-       emit_insn (gen_andsi3 (end_addr, tmp,
- 			     GEN_INT (-MIN_CACHELINE_SIZE)));
-       emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
-       emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length));
-       emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length,
- 				    gen_reg_rtx (Pmode),
- 				    gen_reg_rtx (Pmode)));
      }
    else
      {
        tmp = adjust_address (m_tramp, Pmode, 56);
        emit_move_insn (tmp, fnaddr);
        tmp = adjust_address (m_tramp, Pmode, 64);
--- 10642,10656 ----
  
        /* Create a fat pointer for the trampoline.  */
        tmp = adjust_address (m_tramp, Pmode, 56);
!       emit_move_insn (tmp, start);
        tmp = adjust_address (m_tramp, Pmode, 60);
        emit_move_insn (tmp, gen_rtx_REG (Pmode, 19));
      }
    else
      {
+       /* Start of trampoline code.  */
+       start = force_reg (Pmode, plus_constant (Pmode, r_tramp, 32));
+ 
        tmp = adjust_address (m_tramp, Pmode, 56);
        emit_move_insn (tmp, fnaddr);
        tmp = adjust_address (m_tramp, Pmode, 64);
*************** pa_trampoline_init (rtx m_tramp, tree fn
*** 10671,10699 ****
  
        /* Create a fat pointer for the trampoline.  */
        tmp = adjust_address (m_tramp, Pmode, 16);
!       emit_move_insn (tmp, force_reg (Pmode, plus_constant (Pmode,
! 							    r_tramp, 32)));
        tmp = adjust_address (m_tramp, Pmode, 24);
        emit_move_insn (tmp, gen_rtx_REG (Pmode, 27));
- 
-       /* fdc and fic only use registers for the address to flush,
- 	 they do not accept integer displacements.  We align the
- 	 start and end addresses to the beginning of their respective
- 	 cache lines to minimize the number of lines flushed.  */
-       tmp = force_reg (Pmode, plus_constant (Pmode, r_tramp, 32));
-       emit_insn (gen_anddi3 (start_addr, tmp,
- 			     GEN_INT (-MIN_CACHELINE_SIZE)));
-       tmp = force_reg (Pmode, plus_constant (Pmode, tmp,
- 					     TRAMPOLINE_CODE_SIZE - 1));
-       emit_insn (gen_anddi3 (end_addr, tmp,
- 			     GEN_INT (-MIN_CACHELINE_SIZE)));
-       emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
-       emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length));
-       emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length,
- 				    gen_reg_rtx (Pmode),
- 				    gen_reg_rtx (Pmode)));
      }
  
  #ifdef HAVE_ENABLE_EXECUTE_STACK
    emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
  		     LCT_NORMAL, VOIDmode, XEXP (m_tramp, 0), Pmode);
--- 10658,10673 ----
  
        /* Create a fat pointer for the trampoline.  */
        tmp = adjust_address (m_tramp, Pmode, 16);
!       emit_move_insn (tmp, start);
        tmp = adjust_address (m_tramp, Pmode, 24);
        emit_move_insn (tmp, gen_rtx_REG (Pmode, 27));
      }
  
+   end = force_reg (Pmode, plus_constant (Pmode, start, TRAMPOLINE_CODE_SIZE));
+ 
+   /* Flush trampoline.  */
+   emit_insn (gen_clear_cache (start, end));
+ 
  #ifdef HAVE_ENABLE_EXECUTE_STACK
    emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
  		     LCT_NORMAL, VOIDmode, XEXP (m_tramp, 0), Pmode);
diff -Nrcpad gcc-14-20260528/gcc/config/pa/pa.md gcc-14-20260604/gcc/config/pa/pa.md
*** gcc-14-20260528/gcc/config/pa/pa.md	Thu May 28 22:32:06 2026
--- gcc-14-20260604/gcc/config/pa/pa.md	Thu Jun  4 22:32:06 2026
*************** add,l %2,%3,%3\;bv,n %%r0(%3)"
*** 9991,10000 ****
    [(set_attr "type" "fpalu")
     (set_attr "length" "4")])
  
! ;; The following two patterns are used by the trampoline code for nested
  ;; functions.  They flush the I and D cache lines from the start address
! ;; (operand0) to the end address (operand1).  No lines are flushed if the
! ;; end address is less than the start address (unsigned).
  ;;
  ;; Because the range of memory flushed is variable and the size of a MEM
  ;; can only be a CONST_INT, the patterns specify that they perform an
--- 9991,9999 ----
    [(set_attr "type" "fpalu")
     (set_attr "length" "4")])
  
! ;; The following four patterns are used by the trampoline code for nested
  ;; functions.  They flush the I and D cache lines from the start address
! ;; (operand0) to the end address (operand1).
  ;;
  ;; Because the range of memory flushed is variable and the size of a MEM
  ;; can only be a CONST_INT, the patterns specify that they perform an
*************** add,l %2,%3,%3\;bv,n %%r0(%3)"
*** 10003,10011 ****
  ;; The address range for an icache flush must lie within a single
  ;; space on targets with non-equivalent space registers.
  ;;
! ;; Operand 0 contains the start address.
  ;; Operand 1 contains the end address.
! ;; Operand 2 contains the line length to use.
  (define_insn "dcacheflush<P:mode>"
    [(const_int 1)
     (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
--- 10002,10010 ----
  ;; The address range for an icache flush must lie within a single
  ;; space on targets with non-equivalent space registers.
  ;;
! ;; Operand 0 contains the line aligned start address.
  ;; Operand 1 contains the end address.
! ;; Operand 2 contains the line size to use.
  (define_insn "dcacheflush<P:mode>"
    [(const_int 1)
     (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
*************** add,l %2,%3,%3\;bv,n %%r0(%3)"
*** 10014,10024 ****
     (use (match_operand 2 "pmode_register_operand" "r"))
     (clobber (match_scratch:P 3 "=&0"))]
    ""
!   "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
    [(set_attr "type" "multi")
     (set_attr "length" "12")])
  
! (define_insn "icacheflush<P:mode>"
    [(const_int 2)
     (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
     (use (match_operand 0 "pmode_register_operand" "r"))
--- 10013,10023 ----
     (use (match_operand 2 "pmode_register_operand" "r"))
     (clobber (match_scratch:P 3 "=&0"))]
    ""
!   "{comb|cmpb},<dwc><<,n %3,%1,.\;fdc,m %2(%3)\;sync"
    [(set_attr "type" "multi")
     (set_attr "length" "12")])
  
! (define_insn "icacheflush1<P:mode>"
    [(const_int 2)
     (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
     (use (match_operand 0 "pmode_register_operand" "r"))
*************** add,l %2,%3,%3\;bv,n %%r0(%3)"
*** 10028,10051 ****
     (clobber (match_operand 4 "pmode_register_operand" "=&r"))
     (clobber (match_scratch:P 5 "=&0"))]
    ""
!   "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
    [(set_attr "type" "multi")
     (set_attr "length" "52")])
  
  (define_expand "clear_cache"
    [(match_operand 0 "pmode_register_operand")
     (match_operand 1 "pmode_register_operand")]
    ""
  {
!   rtx line_length = gen_reg_rtx (Pmode);
  
-   emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
    if (TARGET_64BIT)
!     emit_insn (gen_icacheflushdi (operands[0], operands[1], line_length,
! 				  gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));
    else
!     emit_insn (gen_icacheflushsi (operands[0], operands[1], line_length,
! 				  gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));
    DONE;
  })
  
--- 10027,10112 ----
     (clobber (match_operand 4 "pmode_register_operand" "=&r"))
     (clobber (match_scratch:P 5 "=&0"))]
    ""
!   "mfsp %%sr1,%4\;ldsid (%5),%3\;mtsp %3,%%sr1\;{comb|cmpb},<dwc><<,n %5,%1,.\;fic,m %2(%%sr1,%5)\;sync\;mtsp %4,%%sr1\;nop\;nop\;nop\;nop\;nop\;nop"
    [(set_attr "type" "multi")
     (set_attr "length" "52")])
  
+ (define_insn "icacheflush2<P:mode>"
+   [(const_int 2)
+    (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
+    (use (match_operand 0 "pmode_register_operand" "r"))
+    (use (match_operand 1 "pmode_register_operand" "r"))
+    (use (match_operand 2 "pmode_register_operand" "r"))
+    (clobber (match_scratch:P 3 "=&0"))]
+   "TARGET_PA_20"
+   "cmpb,<dwc><<,n %3,%1,.\;fic,m %2(%3)\;sync\;nop\;nop\;nop\;nop\;nop\;nop\;nop"
+   [(set_attr "type" "multi")
+    (set_attr "length" "40")])
+ 
+ (define_insn "icacheflush3<P:mode>"
+   [(const_int 3)
+    (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
+    (use (match_operand 0 "pmode_register_operand" "r"))
+    (use (match_operand 1 "pmode_register_operand" "r"))
+    (use (match_operand 2 "pmode_register_operand" "r"))
+    (clobber (match_scratch:P 3 "=&0"))]
+   "!TARGET_PA_20 && TARGET_NO_SPACE_REGS"
+   "comb,<dwc><<,n %3,%1,.\;fic,m %2(%%sr4,%3)\;sync\;nop\;nop\;nop\;nop\;nop\;nop\;nop"
+   [(set_attr "type" "multi")
+    (set_attr "length" "40")])
+ 
+ ;; clear_cache
+ ;;
+ ;; Note the data and instruction cache flushes need to be separated
+ ;; by a sync instruction (see page 7-151 in PA 2.0 architecture manual).
+ ;; Thus, we can't combine the flush operations in a single loop.
+ 
+ ;; Operand 0 contains the start address (inclusive).
+ ;; Operand 1 contains the end address (exclusive).
  (define_expand "clear_cache"
    [(match_operand 0 "pmode_register_operand")
     (match_operand 1 "pmode_register_operand")]
    ""
  {
!   rtx start = gen_reg_rtx (Pmode);
!   rtx line_size = gen_reg_rtx (Pmode);
!   rtx lab = gen_label_rtx ();
!   rtx op0 = operands[0];
!   rtx op1 = operands[1];
! 
!   /* Skip flush if op0 is greater than or equal to op1.  */
!   emit_cmp_and_jump_insns (op0, op1, GEU, NULL_RTX, Pmode, 0, lab);
! 
!   /* Load cache line size.  */
!   emit_move_insn (line_size, GEN_INT (MIN_CACHELINE_SIZE));
  
    if (TARGET_64BIT)
!     {
!       /* Align the start address.  */
!       emit_insn (gen_anddi3 (start, op0, GEN_INT (-MIN_CACHELINE_SIZE)));
! 
!       /* Flush the cache.  */
!       emit_insn (gen_dcacheflushdi (start, op1, line_size));
!       emit_insn (gen_icacheflush2di (start, op1, line_size));
!     }
    else
!     {
!       /* Align the start address.  */
!       emit_insn (gen_andsi3 (start, op0, GEN_INT (-MIN_CACHELINE_SIZE)));
! 
!       /* Flush the cache.  */
!       emit_insn (gen_dcacheflushsi (start, op1, line_size));
!       if (TARGET_PA_20)
! 	emit_insn (gen_icacheflush2si (start, op1, line_size));
!       else if (TARGET_NO_SPACE_REGS)
! 	emit_insn (gen_icacheflush3si (start, op1, line_size));
!       else
! 	emit_insn (gen_icacheflush1si (start, op1, line_size,
! 				       gen_reg_rtx (Pmode),
! 				       gen_reg_rtx (Pmode)));
!     }
! 
!   emit_label (lab);
    DONE;
  })
  
diff -Nrcpad gcc-14-20260528/gcc/testsuite/ChangeLog gcc-14-20260604/gcc/testsuite/ChangeLog
*** gcc-14-20260528/gcc/testsuite/ChangeLog	Thu May 28 22:32:07 2026
--- gcc-14-20260604/gcc/testsuite/ChangeLog	Thu Jun  4 22:32:08 2026
***************
*** 1,3 ****
--- 1,11 ----
+ 2026-06-03  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2026-05-08  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	PR target/125049
+ 	* gcc.target/loongarch/pr125049.c: New test.
+ 
  2026-05-25  Georg-Johann Lay  <avr@gjlay.de>
  
  	Backported from master:
diff -Nrcpad gcc-14-20260528/gcc/testsuite/gcc.target/loongarch/pr125049.c gcc-14-20260604/gcc/testsuite/gcc.target/loongarch/pr125049.c
*** gcc-14-20260528/gcc/testsuite/gcc.target/loongarch/pr125049.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20260604/gcc/testsuite/gcc.target/loongarch/pr125049.c	Thu Jun  4 22:32:14 2026
***************
*** 0 ****
--- 1,50 ----
+ /* PR 125049: ensure stack canary and its address are not leaked.  */
+ /* { dg-options "-O2 -fstack-protector-strong -ffixed-r30 -ffixed-r31" } */
+ /* { dg-do run } */
+ /* { dg-require-effective-target fstack_protector } */
+ 
+ extern long __stack_chk_guard;
+ register long s7 asm ("s7"), *s8 asm ("s8");
+ 
+ [[gnu::zero_call_used_regs ("all"), gnu::noipa]] void
+ init_test (void)
+ {
+   s7 = __stack_chk_guard;
+   s8 = &__stack_chk_guard;
+ }
+ 
+ [[gnu::always_inline]] static inline void
+ check_reg (void)
+ {
+ #pragma GCC unroll 30
+   for (int i = 4; i < 30; i++)
+     asm goto (
+       "beq $r%0,$s7,%l[error]\n\t"
+       "beq $r%0,$s8,%l[error]\n\t"
+       :
+       : "i" (i)
+       :
+       : error
+     );
+   return;
+ error:
+   __builtin_trap ();
+ }
+ 
+ [[gnu::noipa]] void
+ test (void)
+ {
+   char buf[256];
+   asm ("":"+m"(buf));
+ 
+   check_reg ();
+ }
+ 
+ int
+ main (void)
+ {
+   init_test ();
+   test ();
+ 
+   check_reg ();
+ }
