diff -Nrcpad gcc-14-20260220/LAST_UPDATED gcc-14-20260227/LAST_UPDATED
*** gcc-14-20260220/LAST_UPDATED	Fri Feb 20 22:32:21 2026
--- gcc-14-20260227/LAST_UPDATED	Fri Feb 27 22:32:18 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-14 revision 4bad4b20f8a625d907448803d3e3486bcb18d104
--- 1 ----
! Obtained from git: releases/gcc-14 revision 22ab869ea08aeaa877676310a1b82481f4eef1ba
diff -Nrcpad gcc-14-20260220/MD5SUMS gcc-14-20260227/MD5SUMS
*** gcc-14-20260220/MD5SUMS	Fri Feb 20 22:32:25 2026
--- gcc-14-20260227/MD5SUMS	Fri Feb 27 22:32:22 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20260220.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-14-20260227.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** fc9280b02bc68e4fb1ef8d51ccc25061  Change
*** 23,29 ****
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--- 23,29 ----
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*** 541,547 ****
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*** 553,559 ****
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--- 553,559 ----
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*************** b933d50718bbf8c37af06c1cabbf8ad7  gcc/ad
*** 2862,2868 ****
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*** 2912,2919 ****
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--- 2912,2919 ----
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*************** ba884745a15d4b194d0ad2e286b0c617  gcc/co
*** 4285,4291 ****
  33ffb3b80383744cc4872c3213e50ac5  gcc/config/loongarch/gnu-user.h
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--- 4285,4291 ----
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*************** ea6cc43b3fa3313db4228947eed2152e  gcc/co
*** 4308,4323 ****
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*************** f41f3240af59c920785f7ad7373f06c9  gcc/lt
*** 6451,6457 ****
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--- 6451,6457 ----
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*************** cae920ee0ecb9f75f85298db508074be  gcc/lt
*** 6466,6472 ****
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--- 6466,6472 ----
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*************** e8a9eb01b9451a357155e7152df1c669  gcc/ta
*** 8062,8068 ****
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--- 8062,8068 ----
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*************** a7add68c69c48bffecd543855bc97366  gcc/te
*** 45697,45702 ****
--- 45697,45704 ----
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*************** dbfbd76701c5c3e6c8ed37ced1ba9cc7  gcc/te
*** 78541,78547 ****
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--- 78543,78549 ----
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*************** a4f83930fb87bd91e5bb42db50c8d318  gcc/te
*** 105208,105213 ****
--- 105210,105216 ----
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*************** d828e38384c506bf5e7d5a3c02725a37  libssp
*** 123814,123820 ****
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! 01975ba8544e84338ff6ffce0e1742ca  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
--- 123817,123823 ----
  7bb3c32ba0a48d1cf785305e1b783eb6  libssp/strncpy-chk.c
  a19c79c1d86436e86b0fee41e6cf6b15  libssp/vsnprintf-chk.c
  145156e880b03115b393070d0ed37be3  libssp/vsprintf-chk.c
! 803719ac7e819aab396f7492fd47118e  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
*************** c6b3be3f7c9e66db91c556f5614ccd86  libstd
*** 124494,124500 ****
  727aabeecf8dea4131488fc7651a947c  libstdc++-v3/include/bits/alloc_traits.h
  0130a22c73e6916ce695d7a65b55e136  libstdc++-v3/include/bits/allocated_ptr.h
  4303dd43fc7d56b49442b413b25dc805  libstdc++-v3/include/bits/allocator.h
! 3d24dacf67c1141ed92f6a25eb1771f4  libstdc++-v3/include/bits/atomic_base.h
  31881a266f280e51758541ba9f12f2c3  libstdc++-v3/include/bits/atomic_futex.h
  670239be1d02c64eb81eb20244729696  libstdc++-v3/include/bits/atomic_timed_wait.h
  9529790962fcc36aa3e8749da4844883  libstdc++-v3/include/bits/atomic_wait.h
--- 124497,124503 ----
  727aabeecf8dea4131488fc7651a947c  libstdc++-v3/include/bits/alloc_traits.h
  0130a22c73e6916ce695d7a65b55e136  libstdc++-v3/include/bits/allocated_ptr.h
  4303dd43fc7d56b49442b413b25dc805  libstdc++-v3/include/bits/allocator.h
! bfbaebc632ef7934f036a51449baf447  libstdc++-v3/include/bits/atomic_base.h
  31881a266f280e51758541ba9f12f2c3  libstdc++-v3/include/bits/atomic_futex.h
  670239be1d02c64eb81eb20244729696  libstdc++-v3/include/bits/atomic_timed_wait.h
  9529790962fcc36aa3e8749da4844883  libstdc++-v3/include/bits/atomic_wait.h
*************** fc443edc98096342d5fc5be5a9455d4b  libstd
*** 125192,125198 ****
  ad2a7e573743a8dab1111b977e4a80fd  libstdc++-v3/include/std/algorithm
  873395466399e2601facce0f1d3514df  libstdc++-v3/include/std/any
  aab042909edbf7113490e15fccf5b560  libstdc++-v3/include/std/array
! 39d773fd1c85c7ea45e670fb98ceca0c  libstdc++-v3/include/std/atomic
  01cf19d843a4461de3522fe15a305313  libstdc++-v3/include/std/barrier
  b6af1bbc3368d9c5b5a8c7182f8272ec  libstdc++-v3/include/std/bit
  6c83353fc8d46581132ab76a4ff6552a  libstdc++-v3/include/std/bitset
--- 125195,125201 ----
  ad2a7e573743a8dab1111b977e4a80fd  libstdc++-v3/include/std/algorithm
  873395466399e2601facce0f1d3514df  libstdc++-v3/include/std/any
  aab042909edbf7113490e15fccf5b560  libstdc++-v3/include/std/array
! 222b5b2282951760f27dcf4ddcccdaa5  libstdc++-v3/include/std/atomic
  01cf19d843a4461de3522fe15a305313  libstdc++-v3/include/std/barrier
  b6af1bbc3368d9c5b5a8c7182f8272ec  libstdc++-v3/include/std/bit
  6c83353fc8d46581132ab76a4ff6552a  libstdc++-v3/include/std/bitset
*************** c0881d1e2eb764c023ab5b7d8a6c85b7  libstd
*** 132853,132858 ****
--- 132856,132862 ----
  66bdc51662fd70d30902211a53dedff4  libstdc++-v3/testsuite/29_atomics/atomic/cons/single_value.cc
  9e2a8388686f3e26628f06d374c98d11  libstdc++-v3/testsuite/29_atomics/atomic/cons/user_pod.cc
  6eaa7fecae6788d01a20ae43260848b9  libstdc++-v3/testsuite/29_atomics/atomic/cons/value_init.cc
+ 681f32c88b23086d76f165a9e1487576  libstdc++-v3/testsuite/29_atomics/atomic/cons/zero_padding.cc
  4c8038b479383b8690e30cb9dd1b7a3a  libstdc++-v3/testsuite/29_atomics/atomic/is_always_lock_free.cc
  f9b2d6d78dc44c7b8285a07ef1cd9521  libstdc++-v3/testsuite/29_atomics/atomic/lock_free_aliases.cc
  467103d8d6f668882b30ac0653e0cd90  libstdc++-v3/testsuite/29_atomics/atomic/lwg3220.cc
*************** d0fa9f13b49567ec79d8ace05baf270b  libstd
*** 132898,132903 ****
--- 132902,132908 ----
  e9c3082d95bdcf75d84e17829bbbce4f  libstdc++-v3/testsuite/29_atomics/atomic_float/requirements_cxx23.cc
  01b9626b2a289a1c31a5803746520cf9  libstdc++-v3/testsuite/29_atomics/atomic_float/value_init.cc
  4f98204db054b6051e78a00723ddf115  libstdc++-v3/testsuite/29_atomics/atomic_float/wait_notify.cc
+ 25faa0b8cab947a81054c74813773331  libstdc++-v3/testsuite/29_atomics/atomic_float/zero_padding.cc
  280689977a79a773378a128fd3d6cbf0  libstdc++-v3/testsuite/29_atomics/atomic_integral/60940.cc
  9367b35ad862e3e55260981438b3b938  libstdc++-v3/testsuite/29_atomics/atomic_integral/65147.cc
  d673595a1a9a4a12208c70e0c4f4b145  libstdc++-v3/testsuite/29_atomics/atomic_integral/cons/assign_neg.cc
diff -Nrcpad gcc-14-20260220/gcc/ChangeLog gcc-14-20260227/gcc/ChangeLog
*** gcc-14-20260220/gcc/ChangeLog	Fri Feb 20 22:32:05 2026
--- gcc-14-20260227/gcc/ChangeLog	Fri Feb 27 22:32:05 2026
***************
*** 1,3 ****
--- 1,38 ----
+ 2026-02-26  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Revert:
+ 	2025-11-08  Lulu Cheng  <chenglulu@loongson.cn>
+ 
+ 	PR target/122097
+ 	* config/loongarch/loongarch.cc
+ 	(loongarch_const_vector_same_bytes_p): Add processing for
+ 	floating-point vector data.
+ 
+ 2026-02-26  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2026-02-03  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	* config/loongarch/predicates.md (const_vector_neg_fp_operand):
+ 	New define_predicate.
+ 	(reg_or_vector_neg_fp_operand): New define_predicate.
+ 	* config/loongarch/lasx.md (copysign<mode>3): Remove.
+ 	(xorsign<mode>3): Remove.
+ 	* config/loongarch/lsx.md (copysign<mode>3): Remove.
+ 	(@xorsign<mode>3): Remove.
+ 	* config/loongarch/simd.md (copysign<mode>3): New define_expand.
+ 	(@xorsign<mode>3): New define_expand.
+ 	(and<mode>3): Only allow IVEC instead of ALLVEC.
+ 	(ior<mode>3): Likewise.
+ 	(xor<mode>3): Likewise.
+ 	* config/loongarch/loongarch.cc (loongarch_print_operand): No
+ 	longer allow floating-point vector constants for %V.
+ 	(loongarch_const_vector_bitimm_set_p): Always return false for
+ 	floating-point vector constants.
+ 	(loongarch_build_signbit_mask): Factor out force_reg.
+ 	(loongarch_emit_swrsqrtsf): Use integer vector mode instead of
+ 	floating-point vector mode when masking zero inputs.
+ 
  2026-02-18  Martin Jambor  <mjambor@suse.cz>
  
  	PR ipa/106260
diff -Nrcpad gcc-14-20260220/gcc/DATESTAMP gcc-14-20260227/gcc/DATESTAMP
*** gcc-14-20260220/gcc/DATESTAMP	Fri Feb 20 22:32:05 2026
--- gcc-14-20260227/gcc/DATESTAMP	Fri Feb 27 22:32:05 2026
***************
*** 1 ****
! 20260220
--- 1 ----
! 20260227
diff -Nrcpad gcc-14-20260220/gcc/ada/ChangeLog gcc-14-20260227/gcc/ada/ChangeLog
*** gcc-14-20260220/gcc/ada/ChangeLog	Fri Feb 20 22:32:05 2026
--- gcc-14-20260227/gcc/ada/ChangeLog	Fri Feb 27 22:32:05 2026
***************
*** 1,3 ****
--- 1,16 ----
+ 2026-02-25  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/124226
+ 	* sem_res.adb (Resolve_Implicit_Dereference): Move declaration to...
+ 	* sem_res.ads (Resolve_Implicit_Dereference): ...here.
+ 	* sem_attr.adb (Resolve_Attribute) <Attribute_Access>: Also call
+ 	Resolve_Implicit_Dereference when resolving a protected operation.
+ 
+ 2026-02-20  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* libgnat/s-stposu.adb (Finalize_Pool): Pass a local copy of the
+ 	handle in the call to Finalize_And_Deallocate.
+ 
  2026-01-30  Eric Botcazou  <ebotcazou@adacore.com>
  
  	PR ada/123867
diff -Nrcpad gcc-14-20260220/gcc/ada/sem_attr.adb gcc-14-20260227/gcc/ada/sem_attr.adb
*** gcc-14-20260220/gcc/ada/sem_attr.adb	Fri Feb 20 22:32:06 2026
--- gcc-14-20260227/gcc/ada/sem_attr.adb	Fri Feb 27 22:32:06 2026
*************** package body Sem_Attr is
*** 11458,11463 ****
--- 11458,11464 ----
                 end if;
  
                 Resolve (Prefix (P));
+                Resolve_Implicit_Dereference (Prefix (P));
  
                 if not Is_Overloaded (P) then
                    Generate_Reference (Entity (Selector_Name (P)), P);
diff -Nrcpad gcc-14-20260220/gcc/ada/sem_res.adb gcc-14-20260227/gcc/ada/sem_res.adb
*** gcc-14-20260220/gcc/ada/sem_res.adb	Fri Feb 20 22:32:06 2026
--- gcc-14-20260227/gcc/ada/sem_res.adb	Fri Feb 27 22:32:06 2026
*************** package body Sem_Res is
*** 256,267 ****
     --  is the context type, which is used when the operation is a protected
     --  function with no arguments, and the return value is indexed.
  
-    procedure Resolve_Implicit_Dereference (P : Node_Id);
-    --  Called when P is the prefix of an indexed component, or of a selected
-    --  component, or of a slice. If P is of an access type, we unconditionally
-    --  rewrite it as an explicit dereference. This ensures that the expander
-    --  and the code generator have a fully explicit tree to work with.
- 
     procedure Resolve_Intrinsic_Operator (N : Node_Id; Typ : Entity_Id);
     --  A call to a user-defined intrinsic operator is rewritten as a call to
     --  the corresponding predefined operator, with suitable conversions. Note
--- 256,261 ----
diff -Nrcpad gcc-14-20260220/gcc/ada/sem_res.ads gcc-14-20260227/gcc/ada/sem_res.ads
*** gcc-14-20260220/gcc/ada/sem_res.ads	Fri Feb 20 22:32:06 2026
--- gcc-14-20260227/gcc/ada/sem_res.ads	Fri Feb 27 22:32:06 2026
*************** package Sem_Res is
*** 125,130 ****
--- 125,136 ----
     --  own type. For now we assume that the prefix cannot be overloaded and
     --  the name of the entry plays no role in the resolution.
  
+    procedure Resolve_Implicit_Dereference (P : Node_Id);
+    --  Called when P is the prefix of an indexed component, or of a selected
+    --  component, or of a slice. If P is of an access type, we unconditionally
+    --  rewrite it as an explicit dereference. This ensures that the expander
+    --  and the code generator have a fully explicit tree to work with.
+ 
     procedure Resolve_Membership_Equality (N : Node_Id; Typ : Entity_Id);
     --  Resolve the equality operator in an individual membership test
  
diff -Nrcpad gcc-14-20260220/gcc/config/loongarch/lasx.md gcc-14-20260227/gcc/config/loongarch/lasx.md
*** gcc-14-20260220/gcc/config/loongarch/lasx.md	Fri Feb 20 22:32:06 2026
--- gcc-14-20260227/gcc/config/loongarch/lasx.md	Fri Feb 27 22:32:06 2026
***************
*** 2880,2938 ****
    [(set_attr "type" "simd_int_arith")
     (set_attr "mode" "<MODE>")])
  
- (define_expand "copysign<mode>3"
-   [(set (match_dup 4)
- 	(and:FLASX
- 	  (not:FLASX (match_dup 3))
- 	  (match_operand:FLASX 1 "register_operand")))
-    (set (match_dup 5)
- 	(and:FLASX (match_dup 3)
- 		   (match_operand:FLASX 2 "reg_or_vector_same_val_operand")))
-    (set (match_operand:FLASX 0 "register_operand")
- 	(ior:FLASX (match_dup 4) (match_dup 5)))]
-   "ISA_HAS_LASX"
- {
-   /* copysign (x, -1) should instead be expanded as setting the sign
-      bit.  */
-   if (!REG_P (operands[2]))
-     {
-       rtx op2_elt = unwrap_const_vec_duplicate (operands[2]);
-       if (GET_CODE (op2_elt) == CONST_DOUBLE
- 	  && real_isneg (CONST_DOUBLE_REAL_VALUE (op2_elt)))
- 	{
- 	  rtx n = GEN_INT (8 * GET_MODE_SIZE (<UNITMODE>mode) - 1);
- 	  operands[0] = lowpart_subreg (<VIMODE256>mode, operands[0],
- 					<MODE>mode);
- 	  operands[1] = lowpart_subreg (<VIMODE256>mode, operands[1],
- 					<MODE>mode);
- 	  emit_insn (gen_lasx_xvbitseti_<lasxfmt> (operands[0],
- 						   operands[1], n));
- 	  DONE;
- 	}
-     }
- 
-   operands[2] = force_reg (<MODE>mode, operands[2]);
-   operands[3] = loongarch_build_signbit_mask (<MODE>mode, 1, 0);
- 
-   operands[4] = gen_reg_rtx (<MODE>mode);
-   operands[5] = gen_reg_rtx (<MODE>mode);
- })
- 
- (define_expand "xorsign<mode>3"
-   [(set (match_dup 4)
-     (and:FLASX (match_dup 3)
-         (match_operand:FLASX 2 "register_operand")))
-    (set (match_operand:FLASX 0 "register_operand")
-     (xor:FLASX (match_dup 4)
-          (match_operand:FLASX 1 "register_operand")))]
-   "ISA_HAS_LASX"
- {
-   operands[3] = loongarch_build_signbit_mask (<MODE>mode, 1, 0);
- 
-   operands[4] = gen_reg_rtx (<MODE>mode);
- })
- 
- 
  (define_insn "absv4df2"
    [(set (match_operand:V4DF 0 "register_operand" "=f")
  	(abs:V4DF (match_operand:V4DF 1 "register_operand" "f")))]
--- 2880,2885 ----
diff -Nrcpad gcc-14-20260220/gcc/config/loongarch/loongarch.cc gcc-14-20260227/gcc/config/loongarch/loongarch.cc
*** gcc-14-20260220/gcc/config/loongarch/loongarch.cc	Fri Feb 20 22:32:06 2026
--- gcc-14-20260227/gcc/config/loongarch/loongarch.cc	Fri Feb 27 22:32:06 2026
*************** loongarch_const_vector_bitimm_set_p (rtx
*** 1722,1749 ****
        && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
  	  || GET_MODE_CLASS (mode) == MODE_VECTOR_INT))
      {
!       unsigned HOST_WIDE_INT val;
! 
!       if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
! 	{
! 	  rtx val_s = CONST_VECTOR_ELT (op, 0);
! 	  const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (val_s);
! 	  if (GET_MODE (val_s) == DFmode)
! 	    {
! 	      long tmp[2];
! 	      REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp);
! 	      val = (unsigned HOST_WIDE_INT) tmp[1] << 32 | tmp[0];
! 	    }
! 	  else
! 	    {
! 	      long tmp;
! 	      REAL_VALUE_TO_TARGET_SINGLE (*x, tmp);
! 	      val = (unsigned HOST_WIDE_INT) tmp;
! 	    }
! 	}
!       else
! 	val = UINTVAL (CONST_VECTOR_ELT (op, 0));
! 
        int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
  
        if (vlog2 != -1)
--- 1722,1728 ----
        && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
  	  || GET_MODE_CLASS (mode) == MODE_VECTOR_INT))
      {
!       unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0));
        int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
  
        if (vlog2 != -1)
*************** loongarch_const_vector_same_bytes_p (rtx
*** 1835,1861 ****
  
    first = CONST_VECTOR_ELT (op, 0);
    bytes = GET_MODE_UNIT_SIZE (mode);
! 
!   if (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
!     {
!       rtx val_s = CONST_VECTOR_ELT (op, 0);
!       const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (val_s);
!       if (GET_MODE (val_s) == DFmode)
! 	{
! 	  long tmp[2];
! 	  REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp);
! 	  val = (unsigned HOST_WIDE_INT) tmp[1] << 32 | tmp[0];
! 	}
!       else
! 	{
! 	  long tmp;
! 	  REAL_VALUE_TO_TARGET_SINGLE (*x, tmp);
! 	  val = (unsigned HOST_WIDE_INT) tmp;
! 	}
!     }
!   else
!     val = UINTVAL (first);
! 
    first_byte = val & 0xff;
    for (i = 1; i < bytes; i++)
      {
--- 1814,1820 ----
  
    first = CONST_VECTOR_ELT (op, 0);
    bytes = GET_MODE_UNIT_SIZE (mode);
!   val = INTVAL (first);
    first_byte = val & 0xff;
    for (i = 1; i < bytes; i++)
      {
*************** loongarch_print_operand (FILE *file, rtx
*** 6324,6358 ****
  	{
  	  machine_mode mode = GET_MODE_INNER (GET_MODE (op));
  	  rtx val_s = CONST_VECTOR_ELT (op, 0);
! 	  unsigned HOST_WIDE_INT val;
! 
! 	  if (GET_MODE_CLASS (mode) == MODE_FLOAT)
  	    {
! 	      const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (val_s);
! 	      if (GET_MODE (val_s) == DFmode)
! 		{
! 		  long tmp[2];
! 		  REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp);
! 		  val = (unsigned HOST_WIDE_INT) (tmp[1] << 32 | tmp[0]);
! 		}
! 	      else
  		{
! 		  long tmp;
! 		  REAL_VALUE_TO_TARGET_SINGLE (*x, tmp);
! 		  val = (unsigned HOST_WIDE_INT) tmp;
  		}
  	    }
- 	  else
- 	    val = UINTVAL (val_s);
- 
- 	  int vlog2 = exact_log2 (val & GET_MODE_MASK (mode));
- 	  if (vlog2 != -1)
- 	    fprintf (file, "%d", vlog2);
- 	  else
- 	    output_operand_lossage ("invalid use of '%%%c'", letter);
  	}
!       else
! 	output_operand_lossage ("invalid use of '%%%c'", letter);
        break;
  
      case 'W':
--- 6283,6300 ----
  	{
  	  machine_mode mode = GET_MODE_INNER (GET_MODE (op));
  	  rtx val_s = CONST_VECTOR_ELT (op, 0);
! 	  if (CONST_INT_P (val_s))
  	    {
! 	      unsigned HOST_WIDE_INT val = UINTVAL (val_s);
! 	      int vlog2 = exact_log2 (val & GET_MODE_MASK (mode));
! 	      if (vlog2 != -1)
  		{
! 		  fprintf (file, "%d", vlog2);
! 		  break;
  		}
  	    }
  	}
!       output_operand_lossage ("invalid use of '%%%c'", letter);
        break;
  
      case 'W':
*************** loongarch_build_signbit_mask (machine_mo
*** 10767,10773 ****
      return force_reg (inner_mode, mask);
  
    v = loongarch_build_const_vector (vec_mode, vect, mask);
!   return force_reg (vec_mode, v);
  }
  
  /* Use rsqrte instruction and Newton-Rhapson to compute the approximation of
--- 10709,10715 ----
      return force_reg (inner_mode, mask);
  
    v = loongarch_build_const_vector (vec_mode, vect, mask);
!   return v;
  }
  
  /* Use rsqrte instruction and Newton-Rhapson to compute the approximation of
*************** void loongarch_emit_swrsqrtsf (rtx res,
*** 10816,10825 ****
        if (VECTOR_MODE_P (mode))
  	{
  	  machine_mode imode = related_int_vector_mode (mode).require ();
! 	  rtx mask = gen_reg_rtx (imode);
! 	  emit_insn (gen_rtx_SET (mask, gen_rtx_NE (imode, a, zero)));
! 	  emit_insn (gen_rtx_SET (x0, gen_rtx_AND (mode, x0,
! 						   gen_lowpart (mode, mask))));
  	}
        else
  	{
--- 10758,10768 ----
        if (VECTOR_MODE_P (mode))
  	{
  	  machine_mode imode = related_int_vector_mode (mode).require ();
! 	  rtx mask = force_reg (imode, gen_rtx_NE (imode, a, zero));
! 	  emit_move_insn (gen_lowpart (imode, x0),
! 			  gen_rtx_AND (imode,
! 				       gen_lowpart (imode, x0),
! 				       mask));
  	}
        else
  	{
diff -Nrcpad gcc-14-20260220/gcc/config/loongarch/lsx.md gcc-14-20260227/gcc/config/loongarch/lsx.md
*** gcc-14-20260220/gcc/config/loongarch/lsx.md	Fri Feb 20 22:32:06 2026
--- gcc-14-20260227/gcc/config/loongarch/lsx.md	Fri Feb 27 22:32:06 2026
***************
*** 2558,2616 ****
    [(set_attr "type" "simd_int_arith")
     (set_attr "mode" "<MODE>")])
  
- (define_expand "copysign<mode>3"
-   [(set (match_dup 4)
- 	(and:FLSX
- 	  (not:FLSX (match_dup 3))
- 	  (match_operand:FLSX 1 "register_operand")))
-    (set (match_dup 5)
- 	(and:FLSX (match_dup 3)
- 		  (match_operand:FLSX 2 "reg_or_vector_same_val_operand")))
-    (set (match_operand:FLSX 0 "register_operand")
- 	(ior:FLSX (match_dup 4) (match_dup 5)))]
-   "ISA_HAS_LSX"
- {
-   /* copysign (x, -1) should instead be expanded as setting the sign
-      bit.  */
-   if (!REG_P (operands[2]))
-     {
-       rtx op2_elt = unwrap_const_vec_duplicate (operands[2]);
-       if (GET_CODE (op2_elt) == CONST_DOUBLE
- 	  && real_isneg (CONST_DOUBLE_REAL_VALUE (op2_elt)))
- 	{
- 	  rtx n = GEN_INT (8 * GET_MODE_SIZE (<UNITMODE>mode) - 1);
- 	  operands[0] = lowpart_subreg (<VIMODE>mode, operands[0],
- 					<MODE>mode);
- 	  operands[1] = lowpart_subreg (<VIMODE>mode, operands[1],
- 					<MODE>mode);
- 	  emit_insn (gen_lsx_vbitseti_<lsxfmt> (operands[0], operands[1],
- 						n));
- 	  DONE;
- 	}
-     }
- 
-   operands[2] = force_reg (<MODE>mode, operands[2]);
-   operands[3] = loongarch_build_signbit_mask (<MODE>mode, 1, 0);
- 
-   operands[4] = gen_reg_rtx (<MODE>mode);
-   operands[5] = gen_reg_rtx (<MODE>mode);
- })
- 
- (define_expand "@xorsign<mode>3"
-   [(set (match_dup 4)
-     (and:FLSX (match_dup 3)
-         (match_operand:FLSX 2 "register_operand")))
-    (set (match_operand:FLSX 0 "register_operand")
-     (xor:FLSX (match_dup 4)
-          (match_operand:FLSX 1 "register_operand")))]
-   "ISA_HAS_LSX"
- {
-   operands[3] = loongarch_build_signbit_mask (<MODE>mode, 1, 0);
- 
-   operands[4] = gen_reg_rtx (<MODE>mode);
- })
- 
- 
  (define_insn "absv2df2"
    [(set (match_operand:V2DF 0 "register_operand" "=f")
  	(abs:V2DF (match_operand:V2DF 1 "register_operand" "f")))]
--- 2558,2563 ----
diff -Nrcpad gcc-14-20260220/gcc/config/loongarch/predicates.md gcc-14-20260227/gcc/config/loongarch/predicates.md
*** gcc-14-20260220/gcc/config/loongarch/predicates.md	Fri Feb 20 22:32:06 2026
--- gcc-14-20260227/gcc/config/loongarch/predicates.md	Fri Feb 27 22:32:06 2026
***************
*** 642,647 ****
--- 642,659 ----
    return loongarch_const_vector_same_int_p (op, mode, 0, 63);
  })
  
+ (define_predicate "const_vector_neg_fp_operand"
+   (match_code "const_vector")
+ {
+   machine_mode imode = related_int_vector_mode (mode).require ();
+   rtx mask = loongarch_build_signbit_mask (imode, 1, 0);
+ 
+   op = gen_lowpart (imode, op);
+   return rtx_equal_p (mask,
+ 		      simplify_const_binary_operation (AND, imode, mask,
+ 						       op));
+ })
+ 
  (define_predicate "par_const_vector_shf_set_operand"
    (match_code "parallel")
  {
***************
*** 667,669 ****
--- 679,685 ----
  (define_predicate "reg_or_vector_same_uimm6_operand"
    (ior (match_operand 0 "register_operand")
         (match_operand 0 "const_vector_same_uimm6_operand")))
+ 
+ (define_predicate "reg_or_vector_neg_fp_operand"
+   (ior (match_operand 0 "register_operand")
+        (match_operand 0 "const_vector_neg_fp_operand")))
diff -Nrcpad gcc-14-20260220/gcc/config/loongarch/simd.md gcc-14-20260227/gcc/config/loongarch/simd.md
*** gcc-14-20260220/gcc/config/loongarch/simd.md	Fri Feb 20 22:32:06 2026
--- gcc-14-20260227/gcc/config/loongarch/simd.md	Fri Feb 27 22:32:06 2026
***************
*** 500,509 ****
     (set_attr "mode" "<MODE>")])
  
  (define_insn "xor<mode>3"
!   [(set (match_operand:ALLVEC 0 "register_operand" "=f,f,f")
! 	(xor:ALLVEC
! 	  (match_operand:ALLVEC 1 "register_operand" "f,f,f")
! 	  (match_operand:ALLVEC 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
    ""
    "@
     <x>vxor.v\t%<wu>0,%<wu>1,%<wu>2
--- 500,509 ----
     (set_attr "mode" "<MODE>")])
  
  (define_insn "xor<mode>3"
!   [(set (match_operand:IVEC 0 "register_operand" "=f,f,f")
! 	(xor:IVEC
! 	  (match_operand:IVEC 1 "register_operand" "f,f,f")
! 	  (match_operand:IVEC 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
    ""
    "@
     <x>vxor.v\t%<wu>0,%<wu>1,%<wu>2
***************
*** 513,522 ****
     (set_attr "mode" "<MODE>")])
  
  (define_insn "ior<mode>3"
!   [(set (match_operand:ALLVEC 0 "register_operand" "=f,f,f")
! 	(ior:ALLVEC
! 	  (match_operand:ALLVEC 1 "register_operand" "f,f,f")
! 	  (match_operand:ALLVEC 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
    ""
    "@
     <x>vor.v\t%<wu>0,%<wu>1,%<wu>2
--- 513,522 ----
     (set_attr "mode" "<MODE>")])
  
  (define_insn "ior<mode>3"
!   [(set (match_operand:IVEC 0 "register_operand" "=f,f,f")
! 	(ior:IVEC
! 	  (match_operand:IVEC 1 "register_operand" "f,f,f")
! 	  (match_operand:IVEC 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
    ""
    "@
     <x>vor.v\t%<wu>0,%<wu>1,%<wu>2
***************
*** 526,535 ****
     (set_attr "mode" "<MODE>")])
  
  (define_insn "and<mode>3"
!   [(set (match_operand:ALLVEC 0 "register_operand" "=f,f,f")
! 	(and:ALLVEC
! 	  (match_operand:ALLVEC 1 "register_operand" "f,f,f")
! 	  (match_operand:ALLVEC 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))]
    ""
  {
    switch (which_alternative)
--- 526,535 ----
     (set_attr "mode" "<MODE>")])
  
  (define_insn "and<mode>3"
!   [(set (match_operand:IVEC 0 "register_operand" "=f,f,f")
! 	(and:IVEC
! 	  (match_operand:IVEC 1 "register_operand" "f,f,f")
! 	  (match_operand:IVEC 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))]
    ""
  {
    switch (which_alternative)
***************
*** 538,564 ****
        return "<x>vand.v\t%<wu>0,%<wu>1,%<wu>2";
      case 1:
        {
! 	rtx elt0 = CONST_VECTOR_ELT (operands[2], 0);
! 	unsigned HOST_WIDE_INT val;
! 	if (GET_MODE_CLASS (<MODE>mode) == MODE_VECTOR_FLOAT)
! 	  {
! 	  const REAL_VALUE_TYPE *x = CONST_DOUBLE_REAL_VALUE (elt0);
! 	  if (GET_MODE (elt0) == DFmode)
! 	    {
! 	      long tmp[2];
! 	      REAL_VALUE_TO_TARGET_DOUBLE (*x, tmp);
! 	      val = ~((unsigned HOST_WIDE_INT) tmp[1] << 32 | tmp[0]);
! 	    }
! 	  else
! 	    {
! 	      long tmp;
! 	      REAL_VALUE_TO_TARGET_SINGLE (*x, tmp);
! 	      val = ~((unsigned HOST_WIDE_INT) tmp);
! 	    }
! 	  }
! 	else
! 	  val = ~UINTVAL (elt0);
! 	operands[2] = loongarch_gen_const_int_vector (<VIMODE>mode, val & (-val));
  	return "<x>vbitclri.%v0\t%<wu>0,%<wu>1,%V2";
        }
      case 2:
--- 538,546 ----
        return "<x>vand.v\t%<wu>0,%<wu>1,%<wu>2";
      case 1:
        {
! 	operands[2] = simplify_const_unary_operation (NOT, <MODE>mode,
! 						      operands[2],
! 						      <MODE>mode);
  	return "<x>vbitclri.%v0\t%<wu>0,%<wu>1,%V2";
        }
      case 2:
***************
*** 570,575 ****
--- 552,603 ----
    [(set_attr "type" "simd_logic,simd_bit,simd_logic")
     (set_attr "mode" "<MODE>")])
  
+ (define_expand "copysign<mode>3"
+   [(match_operand:FVEC 0 "register_operand")
+    (match_operand:FVEC 1 "register_operand")
+    (match_operand:FVEC 2 "reg_or_vector_neg_fp_operand")]
+   ""
+ {
+   machine_mode imode = <VIMODE>mode;
+   rtx op[3], mask = loongarch_build_signbit_mask (imode, 1, 0);
+ 
+   /* Pun the operation into fixed-point bitwise operations.  */
+   for (int i = 0; i < 3; i++)
+     op[i] = lowpart_subreg (imode, operands[i], <MODE>mode);
+ 
+   /* Copysign from a positive const should have been already simplified
+      to abs, ignore the case here.  Copysign from a negative const is
+      a simple vbitset which is an alternative of ior (see above).  */
+   if (const_vector_neg_fp_operand (operands[2], <MODE>mode))
+     emit_insn (gen_ior<vimode>3 (op[0], op[1], mask));
+   else
+     {
+       mask = force_reg (imode, mask);
+       emit_insn (gen_<simd_isa>_<x>vbitsel_<simdfmt_as_i> (op[0], op[1],
+ 							   op[2], mask));
+     }
+ 
+   DONE;
+ })
+ 
+ (define_expand "@xorsign<mode>3"
+   [(match_operand:FVEC 0 "register_operand")
+    (match_operand:FVEC 1 "register_operand")
+    (match_operand:FVEC 2 "register_operand")]
+   ""
+ {
+   machine_mode imode = <VIMODE>mode;
+   rtx op[3];
+ 
+   for (int i = 0; i < 3; i++)
+     op[i] = lowpart_subreg (imode, operands[i], <MODE>mode);
+ 
+   rtx t = loongarch_build_signbit_mask (imode, 1, 0);
+   t = force_reg (imode, simplify_gen_binary (AND, imode, op[2], t));
+   emit_move_insn (op[0], simplify_gen_binary (XOR, imode, op[1], t));
+   DONE;
+ })
+ 
  ; The LoongArch SX Instructions.
  (include "lsx.md")
  
diff -Nrcpad gcc-14-20260220/gcc/lto/ChangeLog gcc-14-20260227/gcc/lto/ChangeLog
*** gcc-14-20260220/gcc/lto/ChangeLog	Fri Feb 20 22:32:07 2026
--- gcc-14-20260227/gcc/lto/ChangeLog	Fri Feb 27 22:32:07 2026
***************
*** 1,3 ****
--- 1,12 ----
+ 2026-02-26  Michal Jires  <mjires@suse.cz>
+ 
+ 	Backported from master:
+ 	2026-01-11  Michal Jires  <mjires@suse.cz>
+ 
+ 	PR lto/121588
+ 	* lto-symtab.cc (lto_symtab_merge_symbols): Set body_removed
+ 	for symbols resolved outside of IR.
+ 
  2025-12-03  Siddhesh Poyarekar  <siddhesh@gotplt.org>
  
  	Backported from master:
diff -Nrcpad gcc-14-20260220/gcc/lto/lto-symtab.cc gcc-14-20260227/gcc/lto/lto-symtab.cc
*** gcc-14-20260220/gcc/lto/lto-symtab.cc	Fri Feb 20 22:32:07 2026
--- gcc-14-20260227/gcc/lto/lto-symtab.cc	Fri Feb 27 22:32:07 2026
*************** lto_symtab_merge_symbols (void)
*** 1040,1045 ****
--- 1040,1046 ----
  		      node->analyzed = node->definition = false;
  		      node->remove_all_references ();
  		    }
+ 		  node->body_removed = true;
  		}
  	      DECL_EXTERNAL (node->decl) = 1;
  	    }
diff -Nrcpad gcc-14-20260220/gcc/testsuite/ChangeLog gcc-14-20260227/gcc/testsuite/ChangeLog
*** gcc-14-20260220/gcc/testsuite/ChangeLog	Fri Feb 20 22:32:08 2026
--- gcc-14-20260227/gcc/testsuite/ChangeLog	Fri Feb 27 22:32:07 2026
***************
*** 1,3 ****
--- 1,16 ----
+ 2026-02-26  Michal Jires  <mjires@suse.cz>
+ 
+ 	Backported from master:
+ 	2026-01-11  Michal Jires  <mjires@suse.cz>
+ 
+ 	PR lto/121588
+ 	* gcc.dg/lto/attr-weakref-2_0.c: New test.
+ 	* gcc.dg/lto/attr-weakref-2_1.c: New test.
+ 
+ 2026-02-25  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/protected_deref1.adb: New test.
+ 
  2026-02-18  Martin Jambor  <mjambor@suse.cz>
  
  	PR ipa/106260
diff -Nrcpad gcc-14-20260220/gcc/testsuite/gcc.dg/lto/attr-weakref-2_0.c gcc-14-20260227/gcc/testsuite/gcc.dg/lto/attr-weakref-2_0.c
*** gcc-14-20260220/gcc/testsuite/gcc.dg/lto/attr-weakref-2_0.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20260227/gcc/testsuite/gcc.dg/lto/attr-weakref-2_0.c	Fri Feb 27 22:32:09 2026
***************
*** 0 ****
--- 1,11 ----
+ /* { dg-lto-do link } */
+ /* { dg-lto-options {{-O2 -flto}} } */
+ 
+ #define __weak __attribute__((__weak__))
+ void __weak other() {}
+ void __weak fn() {}
+ 
+ int main() {
+   fn();
+   other();
+ }
diff -Nrcpad gcc-14-20260220/gcc/testsuite/gcc.dg/lto/attr-weakref-2_1.c gcc-14-20260227/gcc/testsuite/gcc.dg/lto/attr-weakref-2_1.c
*** gcc-14-20260220/gcc/testsuite/gcc.dg/lto/attr-weakref-2_1.c	Thu Jan  1 00:00:00 1970
--- gcc-14-20260227/gcc/testsuite/gcc.dg/lto/attr-weakref-2_1.c	Fri Feb 27 22:32:09 2026
***************
*** 0 ****
--- 1,3 ----
+ /* { dg-options {{-fno-lto}} } */
+ 
+ void fn() {}
diff -Nrcpad gcc-14-20260220/gcc/testsuite/gcc.target/loongarch/pr122097.c gcc-14-20260227/gcc/testsuite/gcc.target/loongarch/pr122097.c
*** gcc-14-20260220/gcc/testsuite/gcc.target/loongarch/pr122097.c	Fri Feb 20 22:32:14 2026
--- gcc-14-20260227/gcc/testsuite/gcc.target/loongarch/pr122097.c	Fri Feb 27 22:32:11 2026
***************
*** 1,6 ****
  /* { dg-do compile } */
  /* { dg-options "-O3 -mabi=lp64d -mlsx" } */
- /* { dg-final { scan-assembler "vbitseti\.d\t\\\$vr\[0-9\]+,\\\$vr\[0-9\]+,63" } } */
  
  typedef long unsigned int size_t;
  typedef unsigned char simde__mmask8;
--- 1,5 ----
diff -Nrcpad gcc-14-20260220/gcc/testsuite/gnat.dg/protected_deref1.adb gcc-14-20260227/gcc/testsuite/gnat.dg/protected_deref1.adb
*** gcc-14-20260220/gcc/testsuite/gnat.dg/protected_deref1.adb	Thu Jan  1 00:00:00 1970
--- gcc-14-20260227/gcc/testsuite/gnat.dg/protected_deref1.adb	Fri Feb 27 22:32:12 2026
***************
*** 0 ****
--- 1,32 ----
+ -- { dg-do run }
+ 
+ with Ada.Text_IO;
+ 
+ procedure Protected_Deref1 is
+ 
+    protected type Fallback_Hit_Counter_Type is
+       procedure Handler;
+    end Fallback_Hit_Counter_Type;
+ 
+    protected body Fallback_Hit_Counter_Type is
+       procedure Handler is
+       begin
+          Ada.Text_IO.Put_Line ("Test");
+       end Handler;
+    end Fallback_Hit_Counter_Type;
+ 
+    Fallback_Hit_Counter : access Fallback_Hit_Counter_Type :=
+      new Fallback_Hit_Counter_Type;
+ 
+    type X is access protected procedure;
+ 
+    A : X := Fallback_Hit_Counter.all.Handler'Access;
+    B : X := Fallback_Hit_Counter.Handler'Access;
+ 
+ begin
+    A.all;
+    B.all;
+    if A /= B then
+       raise Program_Error;
+    end if;
+ end;
diff -Nrcpad gcc-14-20260220/libstdc++-v3/ChangeLog gcc-14-20260227/libstdc++-v3/ChangeLog
*** gcc-14-20260220/libstdc++-v3/ChangeLog	Fri Feb 20 22:32:17 2026
--- gcc-14-20260227/libstdc++-v3/ChangeLog	Fri Feb 27 22:32:14 2026
***************
*** 1,3 ****
--- 1,19 ----
+ 2026-02-26  Tomasz Kamiński  <tkaminsk@redhat.com>
+ 
+ 	PR libstdc++/123875
+ 	* include/bits/atomic_base.h (__atomic_impl::__clear_padding):
+ 	Use if constexpr unconditionally.
+ 	(__atomic_float<_Fp>::__atomic_float(_Fp)): Skip __clear_padding
+ 	call for constant evaluation.
+ 	* include/std/atomic (atomic<_Tp>::atomic(_Tp)): Likewise.
+ 	* testsuite/29_atomics/atomic/cons/zero_padding.cc: New test.
+ 	* testsuite/29_atomics/atomic_float/zero_padding.cc: New test.
+ 	(cherry picked from commits
+ 	6b550d69fe7cb62ea6e240ce7a4ba29ce33aa1b1
+ 	682c95b808724e6f876ea709b873ac6771704d7b
+ 	060d7c2a9c1fe16d23d98a74287fdb7c73ddb784
+ 	f3ba5ad088cebe117f857329a35b95d18d97a808)
+ 
  2026-02-10  Jonathan Wakely  <jwakely@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-14-20260220/libstdc++-v3/include/bits/atomic_base.h gcc-14-20260227/libstdc++-v3/include/bits/atomic_base.h
*** gcc-14-20260220/libstdc++-v3/include/bits/atomic_base.h	Fri Feb 20 22:32:18 2026
--- gcc-14-20260227/libstdc++-v3/include/bits/atomic_base.h	Fri Feb 27 22:32:15 2026
*************** _GLIBCXX_BEGIN_NAMESPACE_VERSION
*** 964,976 ****
  #endif
        }
  
      template<typename _Tp>
        _GLIBCXX_ALWAYS_INLINE _GLIBCXX14_CONSTEXPR _Tp*
        __clear_padding(_Tp& __val) noexcept
        {
  	auto* __ptr = std::__addressof(__val);
  #if __has_builtin(__builtin_clear_padding)
! 	if _GLIBCXX17_CONSTEXPR (__atomic_impl::__maybe_has_padding<_Tp>())
  	  __builtin_clear_padding(__ptr);
  #endif
  	return __ptr;
--- 964,979 ----
  #endif
        }
  
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wc++17-extensions"
+ 
      template<typename _Tp>
        _GLIBCXX_ALWAYS_INLINE _GLIBCXX14_CONSTEXPR _Tp*
        __clear_padding(_Tp& __val) noexcept
        {
  	auto* __ptr = std::__addressof(__val);
  #if __has_builtin(__builtin_clear_padding)
! 	if constexpr (__atomic_impl::__maybe_has_padding<_Tp>())
  	  __builtin_clear_padding(__ptr);
  #endif
  	return __ptr;
*************** _GLIBCXX_BEGIN_NAMESPACE_VERSION
*** 980,988 ****
      template<typename _Tp>
        using _Val = typename remove_volatile<_Tp>::type;
  
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wc++17-extensions"
- 
      template<bool _AtomicRef = false, typename _Tp>
        _GLIBCXX_ALWAYS_INLINE bool
        __compare_exchange(_Tp& __val, _Val<_Tp>& __e, _Val<_Tp>& __i,
--- 983,988 ----
*************** _GLIBCXX_BEGIN_NAMESPACE_VERSION
*** 1280,1286 ****
  
        constexpr
        __atomic_float(_Fp __t) : _M_fp(__t)
!       { __atomic_impl::__clear_padding(_M_fp); }
  
        __atomic_float(const __atomic_float&) = delete;
        __atomic_float& operator=(const __atomic_float&) = delete;
--- 1280,1289 ----
  
        constexpr
        __atomic_float(_Fp __t) : _M_fp(__t)
!       { 
!  	if (!std::__is_constant_evaluated())
! 	  __atomic_impl::__clear_padding(_M_fp);
!       }
  
        __atomic_float(const __atomic_float&) = delete;
        __atomic_float& operator=(const __atomic_float&) = delete;
diff -Nrcpad gcc-14-20260220/libstdc++-v3/include/std/atomic gcc-14-20260227/libstdc++-v3/include/std/atomic
*** gcc-14-20260220/libstdc++-v3/include/std/atomic	Fri Feb 20 22:32:18 2026
--- gcc-14-20260227/libstdc++-v3/include/std/atomic	Fri Feb 27 22:32:15 2026
*************** _GLIBCXX_BEGIN_NAMESPACE_VERSION
*** 239,245 ****
        {
  #if __cplusplus >= 201402L && __has_builtin(__builtin_clear_padding)
  	if _GLIBCXX17_CONSTEXPR (__atomic_impl::__maybe_has_padding<_Tp>())
! 	  __builtin_clear_padding(std::__addressof(_M_i));
  #endif
        }
  
--- 239,246 ----
        {
  #if __cplusplus >= 201402L && __has_builtin(__builtin_clear_padding)
  	if _GLIBCXX17_CONSTEXPR (__atomic_impl::__maybe_has_padding<_Tp>())
! 	  if (!std::__is_constant_evaluated())
! 	    __builtin_clear_padding(std::__addressof(_M_i));
  #endif
        }
  
diff -Nrcpad gcc-14-20260220/libstdc++-v3/testsuite/29_atomics/atomic/cons/zero_padding.cc gcc-14-20260227/libstdc++-v3/testsuite/29_atomics/atomic/cons/zero_padding.cc
*** gcc-14-20260220/libstdc++-v3/testsuite/29_atomics/atomic/cons/zero_padding.cc	Thu Jan  1 00:00:00 1970
--- gcc-14-20260227/libstdc++-v3/testsuite/29_atomics/atomic/cons/zero_padding.cc	Fri Feb 27 22:32:15 2026
***************
*** 0 ****
--- 1,79 ----
+ // { dg-do run { target c++11 } }
+ // { dg-require-atomic-cmpxchg-word "" }
+ // { dg-add-options libatomic }
+ 
+ #include <atomic>
+ #include <cstring>
+ #include <testsuite_hooks.h>
+ 
+ struct TailPadding { int i; char c; };
+ TailPadding ztail{1, 2}; // zeroed-padding
+ constexpr std::atomic<TailPadding> ctail(TailPadding{1,2});
+ std::atomic<TailPadding> gtail(TailPadding{1,2});
+ 
+ struct MidPadding { char c; int x; };
+ MidPadding zmid{1, 2}; // zeroed-padding
+ constexpr std::atomic<MidPadding> cmid(MidPadding{1,2});
+ std::atomic<MidPadding> gmid(MidPadding{1,2});
+ 
+ struct BitPadding { int : 4; int i : 5; int : 4; int j : 5; int : 4;  };
+ BitPadding zbit{1, 2}; // zeroed-padding
+ constexpr std::atomic<BitPadding> cbit(BitPadding{1,2});
+ std::atomic<BitPadding> gbit(BitPadding{1,2});
+ 
+ struct Ctor
+ {
+   Ctor() = default;
+ 
+   constexpr Ctor(char pc, char pi)
+     : c(pc), i(pi)
+   {}
+ 
+   char c;
+   int i;
+ };
+ 
+ Ctor zctor{1, 2}; // zeroed-padding
+ constexpr std::atomic<Ctor> cctor(Ctor{1,2});
+ std::atomic<Ctor> gctor(Ctor{1,2});
+ 
+ template<typename T>
+ void test_struct(std::atomic<T>& g, const T& zp)
+ {
+   T const d{3, 4};
+   T t;
+ 
+   std::memcpy(&t, &zp, sizeof(T));
+   VERIFY( g.compare_exchange_strong(t, d) );
+ 
+   static std::atomic<T> st(T{1, 2});
+   std::memcpy(&t, &zp, sizeof(T));
+   VERIFY( st.compare_exchange_strong(t, d) );
+ 
+   thread_local std::atomic<T> tl(T{1, 2});
+   std::memcpy(&t, &zp, sizeof(T));
+   VERIFY( tl.compare_exchange_strong(t, d) );
+ 
+   std::atomic<T> l(T{1, 2});
+   std::memcpy(&t, &zp, sizeof(T));
+ #if __cplusplus >= 201402L // Remove once PR114865 is fixed
+   VERIFY( l.compare_exchange_strong(t, d) );
+ #endif
+ 
+   std::atomic<T>* h = new std::atomic<T>(T{1, 2});
+   std::memcpy(&t, &zp, sizeof(T));
+ #if __cplusplus >= 201402L // Remove once PR114865 is fixed
+   VERIFY( h->compare_exchange_strong(t, d) );
+ #endif
+   delete h;
+ 
+   constexpr std::atomic<T> cl(T{1, 2});
+ }
+ 
+ int main()
+ {
+   test_struct(gtail, ztail);
+   test_struct(gmid, zmid);
+   test_struct(gbit, zbit);
+   test_struct(gctor, zctor);
+ }
diff -Nrcpad gcc-14-20260220/libstdc++-v3/testsuite/29_atomics/atomic_float/zero_padding.cc gcc-14-20260227/libstdc++-v3/testsuite/29_atomics/atomic_float/zero_padding.cc
*** gcc-14-20260220/libstdc++-v3/testsuite/29_atomics/atomic_float/zero_padding.cc	Thu Jan  1 00:00:00 1970
--- gcc-14-20260227/libstdc++-v3/testsuite/29_atomics/atomic_float/zero_padding.cc	Fri Feb 27 22:32:15 2026
***************
*** 0 ****
--- 1,45 ----
+ // { dg-do run { target c++20 } }
+ // { dg-require-effective-target libatomic_available }
+ // { dg-additional-options "[atomic_link_flags [get_multilibs]] -latomic" }
+ 
+ #include <atomic>
+ #include <cstring>
+ #include <testsuite_hooks.h>
+ 
+ long double zld(10.5);
+ constexpr std::atomic<long double> cld(10.5);
+ std::atomic<long double> gld(10.5);
+ 
+ template<typename T>
+ void test_floating(std::atomic<T>& g, const T& zp)
+ {
+   T const d = T(7.5);
+   T t;
+ 
+   std::memcpy(&t, &zp, sizeof(T));
+   VERIFY( g.compare_exchange_strong(t, d) );
+ 
+   static std::atomic<T> st(T(10.5));
+   std::memcpy(&t, &zp, sizeof(T));
+   VERIFY( st.compare_exchange_strong(t, d) );
+ 
+   thread_local std::atomic<T> tl(T(10.5));
+   std::memcpy(&t, &zp, sizeof(T));
+   VERIFY( tl.compare_exchange_strong(t, d) );
+ 
+   std::atomic<T> l(T(10.5));
+   std::memcpy(&t, &zp, sizeof(T));
+   VERIFY( l.compare_exchange_strong(t, d) );
+ 
+   std::atomic<T>* h = new std::atomic<T>(T(10.5));
+   std::memcpy(&t, &zp, sizeof(T));
+   VERIFY( h->compare_exchange_strong(t, d) );
+   delete h;
+ 
+   constexpr std::atomic<T> cl(T(10.5));
+ }
+ 
+ int main()
+ {
+   test_floating(gld, zld);
+ }
