diff -Nrcpad gcc-13-20260527/LAST_UPDATED gcc-13-20260603/LAST_UPDATED
*** gcc-13-20260527/LAST_UPDATED	Wed May 27 22:32:17 2026
--- gcc-13-20260603/LAST_UPDATED	Wed Jun  3 22:32:18 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-13 revision c991125a92f0458261e7c46ec2049e3becd3cff0
--- 1 ----
! Obtained from git: releases/gcc-13 revision 80b9a1aee2f9aebba128064669ebb70be0ed9dc3
diff -Nrcpad gcc-13-20260527/MD5SUMS gcc-13-20260603/MD5SUMS
*** gcc-13-20260527/MD5SUMS	Wed May 27 22:32:21 2026
--- gcc-13-20260603/MD5SUMS	Wed Jun  3 22:32:22 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-13-20260527.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-13-20260603.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
*** 21,27 ****
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! e70e386c151f2d2b5d7434c6dbe17011  LAST_UPDATED
  81b3330d422f3ce1ef8b720dfae35068  MAINTAINERS
  2b61ddbd876fa839639a7ca551773426  Makefile.def
  5d2d6a74f897f8158d37f5f2ec6877ce  Makefile.in
--- 21,27 ----
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
  09538b708302f1735f6fa05b622ecf5e  ChangeLog.tree-ssa
  24ab760126489e69436a43185dc3d202  INSTALL/README
! 9e64abb688f21300a1413180c16450f7  LAST_UPDATED
  81b3330d422f3ce1ef8b720dfae35068  MAINTAINERS
  2b61ddbd876fa839639a7ca551773426  Makefile.def
  5d2d6a74f897f8158d37f5f2ec6877ce  Makefile.in
*************** a22e70b3f29292d0e628450f4bb11e62  fixinc
*** 475,481 ****
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! 16ae245450540f9d12a2ba3781e5ad67  gcc/ChangeLog
  a3b63c675afa7a655cc2bfa8a907af79  gcc/ChangeLog-1997
  d9a88529352a010253c2e8fb1ed6023b  gcc/ChangeLog-1998
  240f08f81cb4699e8b49347db38233db  gcc/ChangeLog-1999
--- 475,481 ----
  a916467b91076e631dd8edb7424769c7  gcc/COPYING.LIB
  d32239bcb673463ab874e80d47fae504  gcc/COPYING3
  6a6a8e020838b23406c81b19c1d46df6  gcc/COPYING3.LIB
! b422b625b40e5be883d0ab38fb39d436  gcc/ChangeLog
  a3b63c675afa7a655cc2bfa8a907af79  gcc/ChangeLog-1997
  d9a88529352a010253c2e8fb1ed6023b  gcc/ChangeLog-1998
  240f08f81cb4699e8b49347db38233db  gcc/ChangeLog-1999
*************** fb3fadb88e1d2b3b640cfaaa5ff11780  gcc/Ch
*** 510,516 ****
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! 4b164bf56e651a0b6efd8f18ff758eed  gcc/DATESTAMP
  d41d8cd98f00b204e9800998ecf8427e  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
--- 510,516 ----
  3eb07e0b2e542409bf73d359f7f65609  gcc/ChangeLog.ptr
  e13638e26743ba41e6011b76cc00d9a9  gcc/ChangeLog.tree-ssa
  739ab47f6425bcea1d05e4fc0542de54  gcc/ChangeLog.tuples
! 4123f4b75d8acd8e5dfe47c24216f5a2  gcc/DATESTAMP
  d41d8cd98f00b204e9800998ecf8427e  gcc/DEV-PHASE
  eb92e1ff5e982ca07e173e0eb286d243  gcc/FSFChangeLog
  30e1e33411566388b3164558482dc5e6  gcc/FSFChangeLog.10
*************** c8af08e2d69d3942ed3fa6f40a02be9b  gcc/co
*** 4506,4514 ****
  d6ed3ea0b084fce25b744c74274588a5  gcc/config/pa/pa-openbsd.h
  e90c5d0d138f683915e32d52840e42cc  gcc/config/pa/pa-opts.h
  6d7f17931666ea98e5793e2f41c93ac3  gcc/config/pa/pa-protos.h
! 6a43f63b7f89c5ed6bcfccf2b6f36676  gcc/config/pa/pa.cc
  765c3a4331887e13e7e4d4df4747b59b  gcc/config/pa/pa.h
! f875aa50d58ae06c01348a46110d9c45  gcc/config/pa/pa.md
  20ba6e16f7d2cf5e5eb89348793f2610  gcc/config/pa/pa.opt
  5268cfc61e7af09cd3b9ba6d2fa3faff  gcc/config/pa/pa32-linux.h
  c14312e902452e23e82cf7aea2550044  gcc/config/pa/pa32-netbsd.h
--- 4506,4514 ----
  d6ed3ea0b084fce25b744c74274588a5  gcc/config/pa/pa-openbsd.h
  e90c5d0d138f683915e32d52840e42cc  gcc/config/pa/pa-opts.h
  6d7f17931666ea98e5793e2f41c93ac3  gcc/config/pa/pa-protos.h
! c633d974174bdb76ed46a210048c5ed1  gcc/config/pa/pa.cc
  765c3a4331887e13e7e4d4df4747b59b  gcc/config/pa/pa.h
! f6bd48f3298d21b1fd29bb4bc1aeb436  gcc/config/pa/pa.md
  20ba6e16f7d2cf5e5eb89348793f2610  gcc/config/pa/pa.opt
  5268cfc61e7af09cd3b9ba6d2fa3faff  gcc/config/pa/pa32-linux.h
  c14312e902452e23e82cf7aea2550044  gcc/config/pa/pa32-netbsd.h
*************** b829ed0032c899e107be2db349c913f3  gcc/ta
*** 7637,7643 ****
  811da275a2b9d3186a6decf96c01b0ed  gcc/targhooks.cc
  edb193a32070c4a7626fb75382def9b9  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! cb5fc1d5d907425dffe98f30cbb21197  gcc/testsuite/ChangeLog
  862f04afbd87da2cc6bc432c3f28430f  gcc/testsuite/ChangeLog-1993-2007
  029a5d8dacd25eb5d4711452ac448e5b  gcc/testsuite/ChangeLog-2008
  13ac28c41d51b66b4ec40dba6bd50f39  gcc/testsuite/ChangeLog-2009
--- 7637,7643 ----
  811da275a2b9d3186a6decf96c01b0ed  gcc/targhooks.cc
  edb193a32070c4a7626fb75382def9b9  gcc/targhooks.h
  f39fcaa8197187283ccfed40107b426d  gcc/testsuite/.gitattributes
! 78e88cb4637c3d2478298604109bfb8a  gcc/testsuite/ChangeLog
  862f04afbd87da2cc6bc432c3f28430f  gcc/testsuite/ChangeLog-1993-2007
  029a5d8dacd25eb5d4711452ac448e5b  gcc/testsuite/ChangeLog-2008
  13ac28c41d51b66b4ec40dba6bd50f39  gcc/testsuite/ChangeLog-2009
diff -Nrcpad gcc-13-20260527/gcc/ChangeLog gcc-13-20260603/gcc/ChangeLog
*** gcc-13-20260527/gcc/ChangeLog	Wed May 27 22:32:04 2026
--- gcc-13-20260603/gcc/ChangeLog	Wed Jun  3 22:32:05 2026
***************
*** 1,3 ****
--- 1,12 ----
+ 2026-05-27  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	Backported from master:
+ 	2026-04-15  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	PR tree-optimization/122976
+ 	* tree-sra.cc (path_comparable_for_same_access): Return false if the
+ 	base is a MEM_REF with a different underlying type.
+ 
  2026-05-25  Georg-Johann Lay  <avr@gjlay.de>
  
  	Backported from master:
diff -Nrcpad gcc-13-20260527/gcc/DATESTAMP gcc-13-20260603/gcc/DATESTAMP
*** gcc-13-20260527/gcc/DATESTAMP	Wed May 27 22:32:04 2026
--- gcc-13-20260603/gcc/DATESTAMP	Wed Jun  3 22:32:05 2026
***************
*** 1 ****
! 20260527
--- 1 ----
! 20260602
diff -Nrcpad gcc-13-20260527/gcc/config/pa/pa.cc gcc-13-20260603/gcc/config/pa/pa.cc
*** gcc-13-20260527/gcc/config/pa/pa.cc	Wed May 27 22:32:05 2026
--- gcc-13-20260603/gcc/config/pa/pa.cc	Wed Jun  3 22:32:06 2026
*************** static void
*** 10476,10485 ****
  pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
  {
    rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
!   rtx start_addr = gen_reg_rtx (Pmode);
!   rtx end_addr = gen_reg_rtx (Pmode);
!   rtx line_length = gen_reg_rtx (Pmode);
!   rtx r_tramp, tmp;
  
    emit_block_move (m_tramp, assemble_trampoline_template (),
  		   GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
--- 10476,10482 ----
  pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
  {
    rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
!   rtx start, end, r_tramp, tmp;
  
    emit_block_move (m_tramp, assemble_trampoline_template (),
  		   GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
*************** pa_trampoline_init (rtx m_tramp, tree fn
*** 10487,10492 ****
--- 10484,10492 ----
  
    if (!TARGET_64BIT)
      {
+       /* Start of trampoline code.  */
+       start = r_tramp;
+ 
        tmp = adjust_address (m_tramp, Pmode, 48);
        emit_move_insn (tmp, fnaddr);
        tmp = adjust_address (m_tramp, Pmode, 52);
*************** pa_trampoline_init (rtx m_tramp, tree fn
*** 10494,10521 ****
  
        /* Create a fat pointer for the trampoline.  */
        tmp = adjust_address (m_tramp, Pmode, 56);
!       emit_move_insn (tmp, r_tramp);
        tmp = adjust_address (m_tramp, Pmode, 60);
        emit_move_insn (tmp, gen_rtx_REG (Pmode, 19));
- 
-       /* fdc and fic only use registers for the address to flush,
- 	 they do not accept integer displacements.  We align the
- 	 start and end addresses to the beginning of their respective
- 	 cache lines to minimize the number of lines flushed.  */
-       emit_insn (gen_andsi3 (start_addr, r_tramp,
- 			     GEN_INT (-MIN_CACHELINE_SIZE)));
-       tmp = force_reg (Pmode, plus_constant (Pmode, r_tramp,
- 					     TRAMPOLINE_CODE_SIZE-1));
-       emit_insn (gen_andsi3 (end_addr, tmp,
- 			     GEN_INT (-MIN_CACHELINE_SIZE)));
-       emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
-       emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length));
-       emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length,
- 				    gen_reg_rtx (Pmode),
- 				    gen_reg_rtx (Pmode)));
      }
    else
      {
        tmp = adjust_address (m_tramp, Pmode, 56);
        emit_move_insn (tmp, fnaddr);
        tmp = adjust_address (m_tramp, Pmode, 64);
--- 10494,10508 ----
  
        /* Create a fat pointer for the trampoline.  */
        tmp = adjust_address (m_tramp, Pmode, 56);
!       emit_move_insn (tmp, start);
        tmp = adjust_address (m_tramp, Pmode, 60);
        emit_move_insn (tmp, gen_rtx_REG (Pmode, 19));
      }
    else
      {
+       /* Start of trampoline code.  */
+       start = force_reg (Pmode, plus_constant (Pmode, r_tramp, 32));
+ 
        tmp = adjust_address (m_tramp, Pmode, 56);
        emit_move_insn (tmp, fnaddr);
        tmp = adjust_address (m_tramp, Pmode, 64);
*************** pa_trampoline_init (rtx m_tramp, tree fn
*** 10523,10551 ****
  
        /* Create a fat pointer for the trampoline.  */
        tmp = adjust_address (m_tramp, Pmode, 16);
!       emit_move_insn (tmp, force_reg (Pmode, plus_constant (Pmode,
! 							    r_tramp, 32)));
        tmp = adjust_address (m_tramp, Pmode, 24);
        emit_move_insn (tmp, gen_rtx_REG (Pmode, 27));
- 
-       /* fdc and fic only use registers for the address to flush,
- 	 they do not accept integer displacements.  We align the
- 	 start and end addresses to the beginning of their respective
- 	 cache lines to minimize the number of lines flushed.  */
-       tmp = force_reg (Pmode, plus_constant (Pmode, r_tramp, 32));
-       emit_insn (gen_anddi3 (start_addr, tmp,
- 			     GEN_INT (-MIN_CACHELINE_SIZE)));
-       tmp = force_reg (Pmode, plus_constant (Pmode, tmp,
- 					     TRAMPOLINE_CODE_SIZE - 1));
-       emit_insn (gen_anddi3 (end_addr, tmp,
- 			     GEN_INT (-MIN_CACHELINE_SIZE)));
-       emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
-       emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length));
-       emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length,
- 				    gen_reg_rtx (Pmode),
- 				    gen_reg_rtx (Pmode)));
      }
  
  #ifdef HAVE_ENABLE_EXECUTE_STACK
    emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
  		     LCT_NORMAL, VOIDmode, XEXP (m_tramp, 0), Pmode);
--- 10510,10525 ----
  
        /* Create a fat pointer for the trampoline.  */
        tmp = adjust_address (m_tramp, Pmode, 16);
!       emit_move_insn (tmp, start);
        tmp = adjust_address (m_tramp, Pmode, 24);
        emit_move_insn (tmp, gen_rtx_REG (Pmode, 27));
      }
  
+   end = force_reg (Pmode, plus_constant (Pmode, start, TRAMPOLINE_CODE_SIZE));
+ 
+   /* Flush trampoline.  */
+   emit_insn (gen_clear_cache (start, end));
+ 
  #ifdef HAVE_ENABLE_EXECUTE_STACK
    emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
  		     LCT_NORMAL, VOIDmode, XEXP (m_tramp, 0), Pmode);
diff -Nrcpad gcc-13-20260527/gcc/config/pa/pa.md gcc-13-20260603/gcc/config/pa/pa.md
*** gcc-13-20260527/gcc/config/pa/pa.md	Wed May 27 22:32:05 2026
--- gcc-13-20260603/gcc/config/pa/pa.md	Wed Jun  3 22:32:06 2026
*************** add,l %2,%3,%3\;bv,n %%r0(%3)"
*** 9981,9990 ****
    [(set_attr "type" "fpalu")
     (set_attr "length" "4")])
  
! ;; The following two patterns are used by the trampoline code for nested
  ;; functions.  They flush the I and D cache lines from the start address
! ;; (operand0) to the end address (operand1).  No lines are flushed if the
! ;; end address is less than the start address (unsigned).
  ;;
  ;; Because the range of memory flushed is variable and the size of a MEM
  ;; can only be a CONST_INT, the patterns specify that they perform an
--- 9981,9989 ----
    [(set_attr "type" "fpalu")
     (set_attr "length" "4")])
  
! ;; The following four patterns are used by the trampoline code for nested
  ;; functions.  They flush the I and D cache lines from the start address
! ;; (operand0) to the end address (operand1).
  ;;
  ;; Because the range of memory flushed is variable and the size of a MEM
  ;; can only be a CONST_INT, the patterns specify that they perform an
*************** add,l %2,%3,%3\;bv,n %%r0(%3)"
*** 9993,10001 ****
  ;; The address range for an icache flush must lie within a single
  ;; space on targets with non-equivalent space registers.
  ;;
! ;; Operand 0 contains the start address.
  ;; Operand 1 contains the end address.
! ;; Operand 2 contains the line length to use.
  (define_insn "dcacheflush<P:mode>"
    [(const_int 1)
     (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
--- 9992,10000 ----
  ;; The address range for an icache flush must lie within a single
  ;; space on targets with non-equivalent space registers.
  ;;
! ;; Operand 0 contains the line aligned start address.
  ;; Operand 1 contains the end address.
! ;; Operand 2 contains the line size to use.
  (define_insn "dcacheflush<P:mode>"
    [(const_int 1)
     (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
*************** add,l %2,%3,%3\;bv,n %%r0(%3)"
*** 10004,10014 ****
     (use (match_operand 2 "pmode_register_operand" "r"))
     (clobber (match_scratch:P 3 "=&0"))]
    ""
!   "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
    [(set_attr "type" "multi")
     (set_attr "length" "12")])
  
! (define_insn "icacheflush<P:mode>"
    [(const_int 2)
     (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
     (use (match_operand 0 "pmode_register_operand" "r"))
--- 10003,10013 ----
     (use (match_operand 2 "pmode_register_operand" "r"))
     (clobber (match_scratch:P 3 "=&0"))]
    ""
!   "{comb|cmpb},<dwc><<,n %3,%1,.\;fdc,m %2(%3)\;sync"
    [(set_attr "type" "multi")
     (set_attr "length" "12")])
  
! (define_insn "icacheflush1<P:mode>"
    [(const_int 2)
     (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
     (use (match_operand 0 "pmode_register_operand" "r"))
*************** add,l %2,%3,%3\;bv,n %%r0(%3)"
*** 10018,10027 ****
     (clobber (match_operand 4 "pmode_register_operand" "=&r"))
     (clobber (match_scratch:P 5 "=&0"))]
    ""
!   "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
    [(set_attr "type" "multi")
     (set_attr "length" "52")])
  
  ;; An out-of-line prologue.
  (define_insn "outline_prologue_call"
    [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
--- 10017,10105 ----
     (clobber (match_operand 4 "pmode_register_operand" "=&r"))
     (clobber (match_scratch:P 5 "=&0"))]
    ""
!   "mfsp %%sr1,%4\;ldsid (%5),%3\;mtsp %3,%%sr1\;{comb|cmpb},<dwc><<,n %5,%1,.\;fic,m %2(%%sr1,%5)\;sync\;mtsp %4,%%sr1\;nop\;nop\;nop\;nop\;nop\;nop"
    [(set_attr "type" "multi")
     (set_attr "length" "52")])
  
+ (define_insn "icacheflush2<P:mode>"
+   [(const_int 2)
+    (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
+    (use (match_operand 0 "pmode_register_operand" "r"))
+    (use (match_operand 1 "pmode_register_operand" "r"))
+    (use (match_operand 2 "pmode_register_operand" "r"))
+    (clobber (match_scratch:P 3 "=&0"))]
+   "TARGET_PA_20"
+   "cmpb,<dwc><<,n %3,%1,.\;fic,m %2(%3)\;sync\;nop\;nop\;nop\;nop\;nop\;nop\;nop"
+   [(set_attr "type" "multi")
+    (set_attr "length" "40")])
+ 
+ (define_insn "icacheflush3<P:mode>"
+   [(const_int 3)
+    (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
+    (use (match_operand 0 "pmode_register_operand" "r"))
+    (use (match_operand 1 "pmode_register_operand" "r"))
+    (use (match_operand 2 "pmode_register_operand" "r"))
+    (clobber (match_scratch:P 3 "=&0"))]
+   "!TARGET_PA_20 && TARGET_NO_SPACE_REGS"
+   "comb,<dwc><<,n %3,%1,.\;fic,m %2(%%sr4,%3)\;sync\;nop\;nop\;nop\;nop\;nop\;nop\;nop"
+   [(set_attr "type" "multi")
+    (set_attr "length" "40")])
+ 
+ ;; clear_cache
+ ;;
+ ;; Note the data and instruction cache flushes need to be separated
+ ;; by a sync instruction (see page 7-151 in PA 2.0 architecture manual).
+ ;; Thus, we can't combine the flush operations in a single loop.
+ 
+ ;; Operand 0 contains the start address (inclusive).
+ ;; Operand 1 contains the end address (exclusive).
+ (define_expand "clear_cache"
+   [(match_operand 0 "pmode_register_operand")
+    (match_operand 1 "pmode_register_operand")]
+   ""
+ {
+   rtx start = gen_reg_rtx (Pmode);
+   rtx line_size = gen_reg_rtx (Pmode);
+   rtx lab = gen_label_rtx ();
+   rtx op0 = operands[0];
+   rtx op1 = operands[1];
+ 
+   /* Skip flush if op0 is greater than or equal to op1.  */
+   emit_cmp_and_jump_insns (op0, op1, GEU, NULL_RTX, Pmode, 0, lab);
+ 
+   /* Load cache line size.  */
+   emit_move_insn (line_size, GEN_INT (MIN_CACHELINE_SIZE));
+ 
+   if (TARGET_64BIT)
+     {
+       /* Align the start address.  */
+       emit_insn (gen_anddi3 (start, op0, GEN_INT (-MIN_CACHELINE_SIZE)));
+ 
+       /* Flush the cache.  */
+       emit_insn (gen_dcacheflushdi (start, op1, line_size));
+       emit_insn (gen_icacheflush2di (start, op1, line_size));
+     }
+   else
+     {
+       /* Align the start address.  */
+       emit_insn (gen_andsi3 (start, op0, GEN_INT (-MIN_CACHELINE_SIZE)));
+ 
+       /* Flush the cache.  */
+       emit_insn (gen_dcacheflushsi (start, op1, line_size));
+       if (TARGET_PA_20)
+ 	emit_insn (gen_icacheflush2si (start, op1, line_size));
+       else if (TARGET_NO_SPACE_REGS)
+ 	emit_insn (gen_icacheflush3si (start, op1, line_size));
+       else
+ 	emit_insn (gen_icacheflush1si (start, op1, line_size,
+ 				       gen_reg_rtx (Pmode),
+ 				       gen_reg_rtx (Pmode)));
+     }
+ 
+   emit_label (lab);
+   DONE;
+ })
+ 
  ;; An out-of-line prologue.
  (define_insn "outline_prologue_call"
    [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
diff -Nrcpad gcc-13-20260527/gcc/testsuite/ChangeLog gcc-13-20260603/gcc/testsuite/ChangeLog
*** gcc-13-20260527/gcc/testsuite/ChangeLog	Wed May 27 22:32:07 2026
--- gcc-13-20260603/gcc/testsuite/ChangeLog	Wed Jun  3 22:32:08 2026
***************
*** 1,3 ****
--- 1,11 ----
+ 2026-05-27  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	Backported from master:
+ 	2026-04-15  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	PR tree-optimization/122976
+ 	* gcc.dg/tree-ssa/pr122976.c: New test.
+ 
  2026-05-25  Georg-Johann Lay  <avr@gjlay.de>
  
  	Backported from master:
